JAJSJ18A June   2024  – October 2024 LMH1229 , LMH1239

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements for Serial Management (SM) Bus Interface
    7. 5.7 Timing Requirements for Serial Parallel Interface (SPI) Interface
    8. 5.8 Typical Characteristics
      1. 5.8.1 TX Characteristics
      2. 5.8.2 RX Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 4-Level Input Pins and Thresholds
      2. 6.3.2 Input and Output Signal Flow Control
        1. 6.3.2.1 Input Mux Selection (LMH1239 Only)
        2. 6.3.2.2 Output Mux and SDI_OUT Selection
      3. 6.3.3 Input Carrier Detect
      4. 6.3.4 Adaptive Cable Equalizer (SDI_IN±, SDI_IN1±)
      5. 6.3.5 Clock and Data (CDR) Recovery
      6. 6.3.6 CDR Loop Bandwidth Control
      7. 6.3.7 Output Function Control
      8. 6.3.8 Output Driver Control
        1. 6.3.8.1 Line-Side 75Ω Output Cable Driver (SDI_OUT±)
          1. 6.3.8.1.1 Output Amplitude (VOD)
          2. 6.3.8.1.2 Output Pre-Emphasis
          3. 6.3.8.1.3 Output Slew Rate
          4. 6.3.8.1.4 Output Polarity Inversion
        2. 6.3.8.2 Host-Side 100Ω Output Driver (OUT0±, OUT1±)
      9. 6.3.9 Debug and Diagnostic Features
        1. 6.3.9.1 Internal Eye Opening Monitor (EOM)
        2. 6.3.9.2 PRBS Generator, Error Checker, and Error Injector
        3. 6.3.9.3 Status Indicators and Interrupts
          1. 6.3.9.3.1 LOCK_N (Lock Indicator)
          2. 6.3.9.3.2 CD_N (Carrier Detect)
          3. 6.3.9.3.3 Cable Fault Detection (SDI_OUT+ Only)
          4. 6.3.9.3.4 INT_N (Interrupt)
        4. 6.3.9.4 Additional Programmability
          1. 6.3.9.4.1 Cable EQ Index (CEI)
          2. 6.3.9.4.2 Digital MUTEREF
    4. 6.4 Device Functional Modes
      1. 6.4.1 System Management Bus (SMBus) Mode
        1. 6.4.1.1 SMBus Read and Write Transaction
          1. 6.4.1.1.1 SMBus Write Operation Format
          2. 6.4.1.1.2 SMBus Read Operation Format
      2. 6.4.2 Serial Peripheral Interface (SPI) Mode
        1. 6.4.2.1 SPI Read and Write Transactions
          1. 6.4.2.1.1 SPI Write Transaction Format
          2. 6.4.2.1.2 SPI Read Transaction Format
        2. 6.4.2.2 SPI Daisy Chain
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 SMPTE Requirements and Specifications
      2. 7.1.2 Optimizing the Time to Adapt and Lock
      3. 7.1.3 Optimized Loop Bandwidth Settings for Diagnostic or Cascade Applications
      4. 7.1.4 LMH1229 and LMH1297 (EQ Mode) Pin-to-Pin Compatibility
    2. 7.2 Typical Application
      1. 7.2.1 Cable Equalizer With Loop-Through
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Cable Equalizer With Redundant SDI Input (LMH1239 only)
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
        3. 7.2.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Board Stack-Up and Ground References
        2. 7.4.1.2 High-Speed PCB Trace Routing and Coupling
          1. 7.4.1.2.1 SDI_IN± and SDI_OUT±:
          2. 7.4.1.2.2 OUT0± and OUT1±:
        3. 7.4.1.3 Anti-Pads
        4. 7.4.1.4 BNC Connector Layout and Routing
        5. 7.4.1.5 Power Supply and Ground Connections
        6. 7.4.1.6 Footprint Recommendations
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER
PDACTIVE Power dissipation, measured with PRBS10, CDR locked to 11.88Gbps, VOD = default SDI_OUT± disabled
OUT0± enabled
OUT1± disabled		 350 466 mW
SDI_OUT± disabled
OUT0± enabled
OUT1± enabled		 380 517 mW
SDI_OUT± enabled
OUT0± enabled
OUT1± disabled		 480 640 mW
SDI_OUT± enabled
OUT0± enabled
OUT1± enabled		 520 688 mW
PDZ Power dissipation, power save mode MODE_SEL = High 70 110 mW
PDZ Power dissipation, power save mode with no signal No signal applied at SDI_IN+, MODE_SEL = F or MODE_SEL = Low 75 115 mW
IDDACTIVE Current consumption, measured with PRBS10, CDR locked to 11.88Gbps, VOD = default SDI_OUT± disabled
OUT0± enabled
OUT1± disabled		 140 177 mA
SDI_OUT± disabled
OUT0± enabled
OUT1± enabled		 152 197 mA
SDI_OUT± enabled
OUT0± enabled
OUT1± disabled		 192 244 mA
SDI_OUT± enabled
OUT0± enabled
OUT1± enabled		 208 262 mA
IDDZ Current consumption, power save mode No signal applied at SDI_IN+ 28 42 mA
IDDTRANS Current consumption, CDR acquiring lock SDI_OUT± disabled
OUT0± enabled
OUT1± disabled		 210 268 mA
SDI_OUT± disabled
OUT0± enabled
OUT1± enabled		 230 287 mA
SDI_OUT± enabled
OUT0± enabled
OUT1± disabled		 270 333 mA
SDI_OUT± enabled
OUT0± enabled
OUT1± enabled		 280 353 mA
LVCMOS DC SPECIFICATIONS
VIH Logic high input voltage 2-Level input (CS_N, SCK, PICO, SDI_OUT_SEL, ENABLE) 0.72 × VIN VIN + 0.3 V
2-Level input (SCL, SDA) 0.7 × VIN 3.6 V
VIL Logic Low input voltage 2-Level input (CS_N, SCK, PICO, SDI_OUT_SEL, ENABLE, SCL, SDA) 0 0.3 × VIN V
VOH Logic high output voltage IOH = –2mA, (POCI) 0.8 × VIN VIN V
VOL Logic low output voltage IOL = 2mA, (POCI) 0 0.2 × VIN V
IOL = 3mA, (LOCK_N, SDA) 0.4 V
IIH Input high leakage current
(Vinput = VIN)		 LVCMOS (SDI_OUT_SEL, ENABLE) 15 µA
SPI mode: LVCMOS (CS_N, SCK, PICO) 15 µA
SMBus mode: LVCMOS (SCL, SDA) 15 µA
IIL Input low leakage current
(Vinput = GND)		 LVCMOS (SDI_OUT_SEL, ENABLE) –50 µA
SPI mode: LVCMOS (SCK, PICO) –15 µA
SPI mode: LVCMOS (CS_N) –50 µA
SMBus mode: LVCMOS (SCL, SDA) –10 µA
4-LEVEL LOGIC DC SPECIFICATIONS (APPLY TO ALL 4-LEVEL INPUT CONTROL PINS)
VLVL_H LEVEL-H input voltage Measured voltage at 4-level pin with external 1kΩ to VIN VIN V
VLVL_F LEVEL-F default voltage Measured voltage 4-level pin at default 2/3 × VIN V
V LVL_R LEVEL-R input voltage Measured voltage at 4-level pin with external 20kΩ to VSS 1/3 × VIN V
VLVL_L LEVEL-L input voltage Measured voltage at 4-level pin with external 1kΩ to VSS 0 V
IIH Input high leakage current
(Vinput = VIN)		 4-Levels (LOOP_BW_SEL, IN_MUX_SEL, OUT_MUX_SEL, VOD_DE, MODE_SEL, OUT_CTRL, SDI_VOD) 20 45 80 µA
SMBus mode: 4-levels (ADDR0, ADDR1) 20 45 80 µA
IIL Input low leakage current
(Vinput = GND)		 4-Levels (LOOP_BW_SEL, IN_MUX_SEL, OUT_MUX_SEL, VOD_DE, MODE_SEL, OUT_CTRL, SDI_VOD) –160 –90 –40 µA
SMBus mode: 4-Levels (ADDR0, ADDR1) –160 –90 –40 µA
SDI RECEIVER SPECIFICATIONS (SDI_IN+(4))
RSDI_IN_TERM DC input single-ended termination SDI_IN+ and SDI_IN– to internal common-mode bias 63 75 87 Ω
RLSDI_IN_S11 Input Return Loss at SDI_IN+ reference to 75Ω(1) S11, 5MHz to 1.485GHz –30 dB
S11, 1.485GHz to 3GHz –25 dB
S11, 3GHz to 6GHz –16 dB
S11, 6GHz to 12GHz –13 dB
VSDI_IN_CM SDI_IN+ DC common-mode voltage Input DC common-mode voltage at SDI_IN+ or SDI_IN– to GND 1.4 V
VSDI_IN_WANDER Input DC wander tolerance SD, input signal at SDI_IN+, input launch amplitude = 800mVpp
 150 mVpp
HD, 3G, 6G, 12G, input signal at SDI_IN+, input launch amplitude = 800mVpp
 50 mVpp
ReachPRBS9 Input cable reach with B1694A, measured with LMH1239EVM, OUT1± and SDI_OUT+ disabled Measured at OUT0±, PRBS9 (BER ≤ 1E-12), TX launch amplitude = 800mVpp before cable
11.88Gbps ± 1000ppm (12G-SDI)
 100 m
5.94Gbps ± 1000ppm (6G-SDI) 150 m
2.97Gbps ± 1000ppm (3G) 220 m
1.485Gbps ± 1000ppm (HD) 300 m
270Mbps ± 1000ppm (SD) 600 m
Input cable reach with B1694A, measured with LMH1239EVM, OUT1± and SDI_OUT+ enabled Measured at OUT0±, PRBS9 (BER ≤ 1E-12), TX launch amplitude = 800mVpp before cable
11.88Gbps ± 1000ppm (12G-SDI)
 90 m
5.94Gbps ± 1000ppm (6G-SDI) 140 m
2.97Gbps ± 1000ppm (3G) 220 m
1.485Gbps ± 1000ppm (HD) 300 m
270Mbps ± 1000ppm (SD) 600 m
ReachPATH Input cable reach with B1694A, measured with LMH1239EVM, OUT1± and SDI_OUT+ disabled Measured at OUT0±, Pathological Pattern (BER ≤ 1E-12), TX launch amplitude = 800mVpp before cable
11.88Gbps (12G-SDI)
Test with SDI_IN1+		 90 m
5.94Gbps (6G-SDI) 140 m
2.97Gbps (3G) 220 m
1.485Gbps (HD) 300 m
270Mbps (SD) 600 m
Input cable reach with B1694A, measured with LMH1239EVM, OUT1± and SDI_OUT+ enabled Measured at OUT0±, Pathological Pattern (BER ≤ 1E-12), TX launch amplitude = 800mVpp before cable
11.88Gbps (12G-SDI)
Test with SDI_IN+		 80 m
5.94Gbps (6G-SDI) 140 m
2.97Gbps (3G) 220 m
1.485Gbps (HD) 300 m
270Mbps (SD) 600 m
RECLOCKER CLOCK AND DATA RECOVERY SPECIFICATIONS
LOCKRATE Reclocker lock data rates SMPTE 12G, /1 11.88 Gbps
SMPTE 12G, /1.001 11.868 Gbps
SMPTE 6G, /1 5.94 Gbps
SMPTE 6G, /1.001 5.934 Gbps
SMPTE 3G, /1 2.97 Gbps
SMPTE 3G, /1.001 2.967 Gbps
SMPTE HD, /1 1.485 Gbps
SMPTE HD, /1.001 1.4835 Gbps
SMPTE SD, /1 270 Mbps
BYPASSRATE Reclocker automatically goes to bypass(6) MADI 125 Mbps
BWPLL PLL bandwidth,
LOOP_BW_SEL=F (default)		 Applied 0.2UI input sinusoidal jitter, measure –3dB bandwidth on input-to-output jitter transfer
11.88Gbps		 7 MHz
5.94Gbps 7 MHz
2.97Gbps 5 MHz
1.485Gbps 3 MHz
270Mbps 0.8 MHz
PLL bandwidth,
LOOP_BW_SEL=H(5)		 Applied 0.2UI input sinusoidal jitter, measure –3dB bandwidth on input-to-output jitter transfer
11.88Gbps		 7 MHz
5.94Gbps 7 MHz
2.97Gbps 5 MHz
1.485Gbps 3 MHz
270Mbps 0.8 MHz
PLL bandwidth,
LOOP_BW_SEL=R(5)		 Applied 0.2UI input sinusoidal jitter, measure –3dB bandwidth on input-to-output jitter transfer
11.88Gbps		 0.70 MHz
5.94Gbps 0.60 MHz
2.97Gbps 0.46 MHz
1.485Gbps 0.24 MHz
270Mbps 0.05 MHz
PLL bandwidth,
LOOP_BW_SEL=L(5)		 Applied 0.2UI input sinusoidal jitter, measure –3dB bandwidth on input-to-output jitter transfer
11.88Gbps		 0.35 MHz
5.94Gbps 0.30 MHz
2.97Gbps 0.23 MHz
1.485Gbps 0.12 MHz
270Mbps 0.03 MHz
JPEAK PLL jitter peaking 12G/6G/3G/HD/SD <0.3 dB
JTOL_SDI SDI_IN+ input jitter tolerance Sinusoidal jitter, tested at 12G/6G/3G
SJ amplitude swept from 1MHz to 80MHz, tested at BER ≤ 1E-12, cable equalizer at SDI_IN+ bypassed		 0.55 UI
TLOCK CDR Lock Time SMPTE supported data rates, includes EQ coarse adaptation. Does not include SSLMS adaptation. No external LF capacitor applied. 1.2 4.5 ms
TADAPT EQ adapt time SMPTE supported data rates, includes CDR lock time. No external LF capacitor applied. 1.6 ms
TEMPLOCK VCO temperature lock range Measured with temperature ramp of 5°C per min, ramp up and down, –40°C to 85°C operating range at 11.88Gbps 125 °C
TLATENCY Input-to-output latency (propagation delay) Measured from SDI_IN+ to OUT0, all supported data rates, CDR enabled and locked 2.1 UI + 270 ps
Measured from SDI_IN+ to SDI_OUT+, all supported data rates, CDR enabled and locked 2.1 UI + 255 ps
Measured from SDI_IN+ to OUT0, all supported data rates, raw mode (CDR bypassed) 270 ps
Measured from SDI_IN+ to SDI_OUT+, 12G/6G/3G/HD, raw mode (CDR bypassed), OUT_CTRL = L 255 ps
Measured from SDI_IN+ to SDI_OUT+, SD, raw mode (CDR bypassed), OUT_CTRL = L 900 ps
RECLOCKER DIFFERENTIAL OUTPUT JITTER (OUT0±, OUT1±)
TJDIFF_OUT Total jitter (BER ≤ 1E-12), reclocked output with SDI_OUT disabled(1)(3) Measured at OUT0±, PRBS9, TX launch amplitude = 800mVpp before cable
11.88Gbps: 100m Belden 1694A		 0.12 0.20 UI
5.94Gbps: 150m Belden 1694A 0.08
2.97Gbps: 220m Belden 1694A 0.07
1.485Gbps: 300m Belden 1694A 0.05
270Mbps: 600m Belden 1694A 0.11
Total jitter (BER ≤ 1E-12), reclocked output with SDI_OUT enabled(1)(3) Measured at OUT0±, PRBS9, TX launch amplitude = 800mVpp before cable
11.88Gbps: 90m Belden 1694A		 0.12 0.20 UI
5.94Gbps: 140m Belden 1694A 0.08
2.97Gbps: 220m Belden 1694A 0.07
1.485Gbps: 300m Belden 1694A 0.05
270Mbps: 600m Belden 1694A 0.11
DJDIFF_OUT Deterministic jitter (BER ≤ 1E-12), reclocked output with SDI_OUT disabled(1)(3) Measured at OUT0±, PRBS9, TX launch amplitude = 800mVpp before cable to SDI_IN+
11.88Gbps: 100m Belden 1694A		 35 80 mUI
5.94Gbps: 150m Belden 1694A 26
2.97Gbps: 220m Belden 1694A 16
1.485Gbps: 300m Belden 1694A 20
270Mbps: 600m Belden 1694A 23
Deterministic jitter (BER ≤ 1E-12), reclocked output with SDI_OUT enabled(1)(3) Measured at OUT0±, PRBS9, TX launch amplitude = 800mVpp before cable to SDI_IN+
11.88Gbps: 90m Belden 1694A		 35 80 mUI
5.94Gbps: 140m Belden 1694A 26
2.97Gbps: 220m Belden 1694A 16
1.485Gbps: 300m Belden 1694A 20
270Mbps: 600m Belden 1694A 23
RJDIFF_OUT Random jitter (BER ≤ 1E-12), reclocked output with SDI_OUT disabled(1)(3) Measured at OUT0±, PRBS9, TX launch amplitude = 800mVpp before cable to SDI_IN+
11.88Gbps: 100m Belden 1694A		 6.2 11 mUIrms
5.94Gbps: 150m Belden 1694A 5.3
2.97Gbps: 220m Belden 1694A 5.3
1.485Gbps: 300m Belden 1694A 4.5
270Mbps: 600m Belden 1694 7.8
Random jitter (BER ≤ 1E-12), reclocked output with SDI_OUT enabled(1)(3) Measured at OUT0±, PRBS9, TX launch amplitude = 800mVpp before cable to SDI_IN+
11.88Gbps: 90m Belden 1694A		 6.2 11 mUIrms
5.94Gbps: 1540m Belden 1694A 5.3
2.97Gbps: 220m Belden 1694A 5.3
1.485Gbps: 300m Belden 1694A 4.5
270Mbps: 600m Belden 1694A 7.8
TJRAW Total jitter (BER ≤1E-12) with CDR bypassed Measured at OUT0±, PRBS9, TX launch amplitude = 800mVpp before cable to SDI_IN+
125Mbps: 600m Belden 1694A		 0.2 UI
RECLOCKER SDI OUTPUT JITTER (SDI_OUT+)
AJSDI_OUT Alignment jitter(1) Measured with 12G-SDI at SDI_OUT+
OUT0± and OUT1± disabled		 0.14 UI
TMJSDI_OUT Timing jitter(1) Measured with 12G-SDI at SDI_OUT+
OUT0± and OUT1± disabled		 0.45 UI
DIFFERENTIAL DRIVER OUTPUT (OUT0±, OUT1±)
RDIFF_OUT_TERM DC output differential termination Measured across OUT0+ and OUT0- 80 100 120 Ω
VODDIFF_OUT Output differential voltage Measured with 8T pattern at 11.88Gbps
VOD_DE = H		 410 mVpp
VOD_DE = F 485 560 635 mVpp
VOD_DE = R 635 mVpp
VOD_DE = L 810 mVpp
VODDIFF_OUT_DE Output de-emphasis level Measured with 8T pattern at 11.88Gbps
VOD_DE = H		 410 mVpp
VOD_DE = F 500 mVpp
VOD_DE = R 480 mVpp
VOD_DE = L 400 mVpp
tR/tF Output rise/fall time Measured with 8T Pattern at 11.88Gbps, 20%-80% amplitude 45 ps
RLDIFF_OUT-SDD22 Output differential return loss(1) Measured with the device powered up and outputs a 10MHz clock signal
SDD22, 10MHz to 2.8GHz		 –26 dB
SDD22, 2.8GHz to 6GHz –18 dB
SDD22, 6GHz to 11.1GHz –13 dB
RLDIFF_OUT-SCC22 Output common-mode return loss(1) Measured with the device powered up and outputs a 10MHz clock signal.
SCC22, 10MHz to 4.75GHz		 –14 dB
SCC22, 4.75GHz to 11.1GHz –16 dB
VDIFF_OUT_CM AC common-mode voltage on OUT0±(1) Default setting, PRBS9, 11.88Gbps 7 mVrms
SDI DRIVER OUTPUT (SDI_OUT+)
ROUT_TERM DC output single-ended termination SDI_OUT+ and SDI_OUT– to VIN 63 75 87 Ω
VODCD_OUTP Output single-ended output voltage Measure AC signal at SDI_OUT+, with SDI_OUT- AC terminated with 75Ω. Measured with color bar on Phabrix Qx with 1m B1694A at 11.88Gbps
SDI_VOD=H		 840 mVpp
SDI_VOD=F(3) 720 800 880 mVpp
SDI_VOD=R 880 mVpp
SDI_VOD=L 760 mVpp
VODCD_OUTN Output single-ended output voltage Measure AC signal at SDI_OUT-, with SDI_OUT+ AC terminated with 75Ω. Measured with color bar on Phabrix Qx with 1m B1694A at 11.88Gbps
SDI_VOD=H		 840 mVpp
SDI_VOD=F(3) 720 800 880 mVpp
SDI_VOD=R 880 mVpp
SDI_VOD=L 760 mVpp
PRECD_OUTP Output pre-emphasis Output pre-emphasis boost amplitude at SDI_OUT+, programmed to maximum setting through register, measured at SDI_VOD=F with 8T pattern at 11.88Gbps 2.5 dB
PRECD_OUTP_T Output pre-emphasis duration Output pre-emphasis time duration, measured after 0.5" trace, BNC connector, and 1m B1694A cable with 8T pattern at 11.88Gbps 83 ps
PRECD_OUTN Output pre-emphasis Output pre-emphasis boost amplitude at SDI_OUT–, programmed to maximum setting through register, measured at SDI_VOD=F with 8T pattern at 11.88Gbps 2.5 dB
PRECD_OUTN_T Output pre-emphasis duration Output pre-emphasis time duration, measured after 0.5" trace, BNC connector, and 1m B1694A cable with 8T pattern at 11.88Gbps 83 ps
tR_F_SDI Output rise and fall time(1) Measured with color bar on Phabrix Qx, default VOD, default pre-emphasis
11.88Gbps		 36 ps
5.94Gbps 36 ps
2.97Gbps 60 ps
1.485Gbps 60 ps
270Mbps 520 ps
tR_F_DELTA Output rise/fall time mismatch(1) Measured with color bar on Phabrix Qx, default VOD, default pre-emphasis
11.88Gbps		 5 ps
5.94Gbps 8 ps
2.97Gbps 13 ps
1.485Gbps 53 ps
270Mbps 75 ps
VOVERSHOOT Output overshoot or undershoot(2) Measured with color bar on Phabrix Qx with 1m B1694A at SDI_OUT+, default VOD, default pre-emphasis, 12G 8 %
VDC_OFFSET DC offset Measured with Phabrix Qx with 1m B1694A at SDI_OUT+, 12G/6G/3G/HD/SD ±0.2 V
VDC_WANDER DC wander Measured with real-time scope with 1m B1694A at SDI_OUT+, 12G/6G/3G/HD with pathological pattern 
 13 mV
RLCD_S22 Output return loss at SDI_OUT+ reference to 75Ω(1) S22, 5MHz to 1.485GHz –23 dB
S22, 1.485GHz to 3GHz –16 dB
S22, 3GHz to 6GHz –16 dB
S22, 6GHz to 12GHz –15 dB
(1) This parameter is measured with the LMH1239EVM (Evaluation board for LMH12x9).
(2) VOVERSHOOT overshoot/undershoot maximum measurements are largely affected by the PCB layout and input test pattern. The maximum value specified in Electrical Characteristics for VOVERSHOOT is based on bench evaluation across temperature and supply voltages with the LMH1239EVM.
(3) This limit is ensured by bench characterization and is not production tested.
(4) All specifications characterized with SDI_IN± on LMH1229 are applicable to both SDI_IN± and SDI_IN1± on LMH1239.
(5) External loop filter capacitor required between LF+ and LF- to implement reduced PLL bandwidth.
(6) Reclocker automatically goes into bypass when the LMH12x9 does not lock to a valid LOCKRATE data rate. When bypassed,  LMH12x9 EQ adaptation is disabled and EQ index must be programmed manually (for more information, refer to the LMH12x9 Programming Guide).