JAJSJ53B may   2020  – april 2023 TPD3S713-Q1 , TPD3S713A-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 FAULT Response
      2. 8.3.2 Cable Compensation
        1. 8.3.2.1 Design Procedure
      3. 8.3.3 DP and DM Protection
      4. 8.3.4 VBUS OVP Protection
      5. 8.3.5 Output and DP or DM Discharge
      6. 8.3.6 Overcurrent Protection
      7. 8.3.7 Undervoltage Lockout
      8. 8.3.8 Thermal Sensing
      9. 8.3.9 Current-Limit Setting
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Truth Table (TT)
      2. 8.4.2 Client Mode
      3. 8.4.3 High-Bandwidth Data-Line Switch
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input Capacitance
        2. 9.2.2.2 Output Capacitance
        3. 9.2.2.3 BIAS Capacitance
        4. 9.2.2.4 Output and BIAS TVS
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Mechanical, Packaging, and Orderable Information

8.3.9 Current-Limit Setting

The TPD3S713x-Q1 has two independent current-limit settings that are each adjusted externally with a resistor. The ILIM_HI setting is adjusted with R(ILIM_HI) connected between ILIM_HI and GND. The ILIM_LO setting is adjusted with R(ILIM_LO) connected between ILIM_LO and GND.

The current limit is selected by ILIM_SEL pin. If ILIM_SEL = high, ILIM_HI is selected; if ILIM_SEL = low, ILIM_LO is selected.

The following equation calculates the value of resistor for adjusting the typical current limit (need update):

Equation 3. GUID-F823A4E9-2125-4E06-AB33-AC652414BAAE-low.png

Many applications require that the current limit meet specific tolerance limits. When designing to these tolerance limits, both the tolerance of the TPD3S713x-Q1 current limit and the tolerance of the external adjusting resistor must be taken into account. The following equations approximate the TPD3S713x-Q1 minimum and maximum current limits to within a few milliamperes and are appropriate for design purposes. The equations do not constitute part of TI’s published device specifications for purposes of TI’s product warranty. These equations assume an ideal—no variation—external adjusting resistor. To take resistor tolerance into account, first determine the minimum and maximum resistor values based on its tolerance specifications and use these values in the equations. Because of the inverse relation between the current limit and the adjusting resistor, use the maximum resistor value in the IOS(min) equation and the minimum resistor value in the IOS(max) equation.

Equation 4. GUID-35CE92A2-C7FB-487F-B300-DF4A14EC8EE9-low.png
Equation 5. GUID-83085F6E-F5C5-4552-8A49-2EC349CABABA-low.png
GUID-0A1397AB-71A4-4DB0-9DE5-6F8CE4F85B96-low.pngFigure 8-3 Current-Limit Setting vs Adjusting Resistor

The routing of the traces to the R(ILIM_xx) resistors must have a sufficiently low resistance so as not to affect the current-limit accuracy. The ground connection for the R(ILIM_xx) resistors is also very important. The resistors must reference back to the TPD3S713x-Q1 GND pin. Follow normal board layout practices to ensure that current flow from other parts of the board does not impact the ground potential between the resistors and the TPD3S713x-Q1 GND pin.