JAJSJ53B may   2020  – april 2023 TPD3S713-Q1 , TPD3S713A-Q1

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 FAULT Response
      2. 8.3.2 Cable Compensation
        1. 8.3.2.1 Design Procedure
      3. 8.3.3 DP and DM Protection
      4. 8.3.4 VBUS OVP Protection
      5. 8.3.5 Output and DP or DM Discharge
      6. 8.3.6 Overcurrent Protection
      7. 8.3.7 Undervoltage Lockout
      8. 8.3.8 Thermal Sensing
      9. 8.3.9 Current-Limit Setting
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Truth Table (TT)
      2. 8.4.2 Client Mode
      3. 8.4.3 High-Bandwidth Data-Line Switch
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input Capacitance
        2. 9.2.2.2 Output Capacitance
        3. 9.2.2.3 BIAS Capacitance
        4. 9.2.2.4 Output and BIAS TVS
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Mechanical, Packaging, and Orderable Information

Pin Configuration and Functions

GUID-E78A8F5D-7CE3-42D9-9009-7418ECDF4FD2-low.gifFigure 5-1 RVC Package20-Pin WQFNTop View
Table 5-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
IMON 1 O This pin sources a scaled-down ratio of current through the internal FET. A resistor from this pin to GND converts current to proportional voltage; used as an analog current monitor.
IN 2,3 PWR Input supply voltage; connect a 0.1-µF or greater ceramic capacitor from IN to GND as close to the IC as possible.
DM_OUT 4 I/O DM data line to upstream USB host controller
DP_OUT 5 I/O DP data line to upstream USB host controller
CS 6 O Linear cable compensation current. Connect to divider resistor of front-end dc-dc converter.
EN 7 I Logic-level control input for turning the power and signal switches on or off. When EN is low, the device is disabled, and the signal and power switches are OFF.
ILIM_SEL 8 I Logic-level control input for choosing the current limit resistor and current limit threshold. When ILIM_SEL = High, ILIM_HI resistor is valid; When ILIM_SEL = Low, ILIM_LO resistor is valid.
INT1 9 I Logic-level control input, the device can be set in normal mode or client mode through pin configuration. If INT1 = high, the device is in normal mode; If INT1 = low and ILIM_SEL = Low, the device is in client mode.
INT2 10 I For internal circuit, must connect to ground without a pull down resistor.
GND 11 Ground connection; must be connected externally to the thermal pad.
BIAS 12 PWR Used for IEC protection. Typically, connect a 2.2-µF capacitor to ground and 5.1-kΩ resistor to BUS.
DP_IN 13 I/O DP data line to downstream connector
DM_IN 14 I/O DM data line to downstream connector
BUS 15,16 PWR Power-switch output
NC 17 NC No connect, leave floating or connect to ground.
FAULT 18 O Active-low, open-drain output, asserted during overtemperature, overcurrent, and overvoltage conditions.
ILIM_LO 19 I External resistor used to set the low current-limit threshold, selected by ILIM_SEL pin.
ILIM_HI 20 I External resistor used to set the high current-limit threshold, selected by ILIM_SEL pin.
Thermal pad Thermal pad on the bottom of the package
I = Input, O = Output, I/O = Input and output, PWR = Power