JAJSJ67E may   2020  – july 2023 UCC28782

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
    1.     Pin Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Detailed Pin Description
      1. 8.3.1  BUR Pin (Programmable Burst Mode)
      2. 8.3.2  FB Pin (Feedback Pin)
      3. 8.3.3  REF Pin (Internal 5-V Bias)
      4. 8.3.4  VDD Pin (Device Bias Supply)
      5. 8.3.5  P13 and SWS Pins
      6. 8.3.6  S13 Pin
      7. 8.3.7  IPC Pin (Intelligent Power Control Pin)
      8. 8.3.8  RUN Pin (Driver and Bias Source for Isolator)
      9. 8.3.9  PWMH and AGND Pins
      10. 8.3.10 PWML and PGND Pins
      11. 8.3.11 SET Pin
      12. 8.3.12 RTZ Pin (Sets Delay for Transition Time to Zero)
      13. 8.3.13 RDM Pin (Sets Synthesized Demagnetization Time for ZVS Tuning)
      14. 8.3.14 BIN, BSW, and BGND Pins
      15. 8.3.15 XCD Pin
      16. 8.3.16 CS, VS, and FLT Pins
    4. 8.4 Device Functional Modes
      1. 8.4.1  Adaptive ZVS Control with Auto-Tuning
      2. 8.4.2  Dead-Time Optimization
      3. 8.4.3  EMI Dither and Dither Fading Function
      4. 8.4.4  Control Law across Entire Load Range
      5. 8.4.5  Adaptive Amplitude Modulation (AAM)
      6. 8.4.6  Adaptive Burst Mode (ABM)
      7. 8.4.7  Low Power Mode (LPM)
      8. 8.4.8  First Standby Power Mode (SBP1)
      9. 8.4.9  Second Standby Power Mode (SBP2)
      10. 8.4.10 Startup Sequence
      11. 8.4.11 Survival Mode of VDD (INT_STOP)
      12. 8.4.12 Capacitor Voltage Balancing Function
      13. 8.4.13 Device Functional Modes for Bias Regulator Control
        1. 8.4.13.1 Mitigation of Switching Interaction with ACF Converter
        2. 8.4.13.2 Protection Functions for the Bias Regulator
        3. 8.4.13.3 BIN-Pin Related Protections
        4. 8.4.13.4 BSW-Pin Related Protections
      14. 8.4.14 System Fault Protections
        1. 8.4.14.1  Brown-In and Brown-Out
        2. 8.4.14.2  Output Over-Voltage Protection (OVP)
        3. 8.4.14.3  Input Over Voltage Protection (IOVP)
        4. 8.4.14.4  Over-Temperature Protection (OTP) on FLT Pin
        5. 8.4.14.5  Over-Temperature Protection (OTP) on CS Pin
        6. 8.4.14.6  Programmable Over-Power Protection (OPP)
        7. 8.4.14.7  Peak Power Limit (PPL)
        8. 8.4.14.8  Output Short-Circuit Protection (SCP)
        9. 8.4.14.9  Over-Current Protection (OCP)
        10. 8.4.14.10 External Shutdown
        11. 8.4.14.11 Internal Thermal Shutdown
      15. 8.4.15 Pin Open/Short Protections
        1. 8.4.15.1 Protections on CS pin Fault
        2. 8.4.15.2 Protections on P13 pin Fault
        3. 8.4.15.3 Protections on RDM and RTZ pin Faults
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application Circuit
      1. 9.2.1 Design Requirements for a 65-W USB-PD Adapter Application
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input Bulk Capacitance and Minimum Bulk Voltage
        2. 9.2.2.2 Transformer Calculations
          1. 9.2.2.2.1 Primary-to-Secondary Turns Ratio (NPS)
          2. 9.2.2.2.2 Primary Magnetizing Inductance (LM)
          3. 9.2.2.2.3 Primary Winding Turns (NP)
          4. 9.2.2.2.4 Secondary Winding Turns (NS)
          5. 9.2.2.2.5 Auxiliary Winding Turns (NA)
          6. 9.2.2.2.6 Winding and Magnetic Core Materials
        3. 9.2.2.3 Clamp Capacitor Calculation
          1. 9.2.2.3.1 Primary-Resonance ACF
          2. 9.2.2.3.2 Secondary-Resonance ACF
        4. 9.2.2.4 Bleed-Resistor Calculation
        5. 9.2.2.5 Output Filter Calculation
        6. 9.2.2.6 Calculation of ZVS Sensing Network
        7. 9.2.2.7 Calculation of BUR Pin Resistances
        8. 9.2.2.8 Calculation of Compensation Network
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1  General Considerations
      2. 11.1.2  RDM and RTZ Pins
      3. 11.1.3  SWS Pin
      4. 11.1.4  VS Pin
      5. 11.1.5  BUR Pin
      6. 11.1.6  FB Pin
      7. 11.1.7  CS Pin
      8. 11.1.8  BIN Pin
      9. 11.1.9  BSW Pin
      10. 11.1.10 AGND Pin
      11. 11.1.11 BGND Pin
      12. 11.1.12 PGND Pin
      13. 11.1.13 EP Thermal Pad
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 用語集
  14. 13Mechanical, Packaging, and Orderable Information

8.4.1 Adaptive ZVS Control with Auto-Tuning

Figure 8-18 shows the simplified block diagram explaining the ZVS control of UCC28782. A high-voltage sensing network provides a replica of the switch node voltage waveform (VSW) with a limited “visible” lower voltage range that the SWS pin can handle. The ZVS discriminator identifies the ZVS condition and determines the adjustment direction for the on-time of PWMH (tDM) by detecting if VSW reaches a predetermined ZVS threshold, VTH(SWS), within tZ, where tZ is the targeted zero voltage transition time of VSW controlled by the PWMH-to-PWML dead-time optimizer.

In Figure 8-18, VSW of the current switching cycle in the dashed line has not reached VTH(SWS) after tZ expires. The ZVS discriminator sends a TUNE signal to increase tDM for the next switching cycle in the solid line, such that the negative magnetizing current (IM-) can be increased to bring VSW down to a lower level in the same tZ. After a few switching cycles, the tDM optimizer settles and locks into ZVS operation of the low-side switch (QL). In steady-state, there is a fine adjustment on tDM, which is the least significant bit (LSB) of the ZVS tuning loop. This small change of tDM in each switching cycle is too small to significantly move the ZVS condition away from the desired operating point. Figure 8-19 demonstrates how fast the ZVS control can lock into ZVS operation. Before the ZVS loop is settled, UCC28782 starts in a valley-switching mode as tDM is not long enough to create sufficient IM-. Within 15 switching cycles, the ZVS tuning loop settles and begins toggling tDM with an LSB.

GUID-E4F6A842-85C2-4FDE-BC0D-7324E610ED77-low.gifFigure 8-18 Block Diagram of Adaptive ZVS Control
GUID-E0E7DF1E-4A4F-4813-BF1E-523796F3E13B-low.gifFigure 8-19 Auto-Tuning Process of Adaptive ZVS Control