JAJSJ94B September   2021  – August 2022 LM74722-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Dual Gate Control (GATE, PD)
        1. 8.3.1.1 Reverse Battery Protection (A, C, GATE)
        2. 8.3.1.2 Load Disconnect Switch Control (PD)
        3. 8.3.1.3 Overvoltage Protection and Battery Voltage Sensing (VSNS, SW, OV)
      2. 8.3.2 Boost Regulator
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical 12-V Reverse Battery Protection Application
      1. 9.2.1 Design Requirements for 12-V Battery Protection
        1. 9.2.1.1 Automotive Reverse Battery Protection
          1. 9.2.1.1.1 Input Transient Protection: ISO 7637-2 Pulse 1
          2. 9.2.1.1.2 AC Super Imposed Input Rectification: ISO 16750-2 and LV124 E-06
          3. 9.2.1.1.3 Input Micro-Short Protection: LV124 E-10
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Design Considerations
        2. 9.2.2.2 Boost Converter Components (C2, C3, L1)
        3. 9.2.2.3 Input and Output Capacitance
        4. 9.2.2.4 Hold-Up Capacitance
        5. 9.2.2.5 Overvoltage Protection and Battery Monitor
        6. 9.2.2.6 MOSFET Selection: Blocking MOSFET Q1
        7. 9.2.2.7 MOSFET Selection: Load Disconnect MOSFET Q2
        8. 9.2.2.8 TVS Selection
      3. 9.2.3 Application Curves
    3. 9.3 What to Do and What Not to Do
  10. 10Power Supply Recommendations
    1. 10.1 Transient Protection
    2. 10.2 TVS Selection for 12-V Battery Systems
    3. 10.3 TVS Selection for 24-V Battery Systems
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 サポート・リソース
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

9.2.2.7 MOSFET Selection: Load Disconnect MOSFET Q2

The VDS rating of the MOSFET Q2 must be sufficient to handle the maximum system voltage along with the input transient voltage. For this 12-V design, transient overvoltage events are during suppressed load dump 35 V 400 ms and ISO 7637-2 pulse 2 A 50 V for 50 µs. Further, ISO 7637-2 pulse 3B is a very fast repetitive pulse of 100 V 100 ns that is usually absorbed by the input and output ceramic capacitors. The maximum voltage on the 12-V battery can be limited to < 40 V the minimum recommended input capacitance of 0.1 µF. The 50-V SO 7637-2 pulse 2 A can also be absorbed by input and output capacitors and its amplitude can be reduced to 40-V peak by placing sufficient amount of capacitance at input and output. Choose a MOSFET with ≥ 40-V VDS rating .

The VGS rating of the MOSFET Q2 must be higher than that maximum boost drive output of 15.5 V. FET with VGS absolute maximum rating of +/– 20 VGS is selected.

Inrush current through the MOSFET during input hot-plug into the 12-V battery is determined by output capacitance. External capacitor on HGATE, CDVDT, is used to limit the inrush current during input hot-plug or start-up. The value of inrush current determined by Equation 1 must be selected to ensure that the MOSFET Q2 is operating well within its safe operating area (SOA). To limit inrush current to 250 mA, value of CDVDT is 10.43 nF. The closest standard value of 10.0 nF is chosen.

Duration of inrush current is calculated by Equation 6

Equation 6.

Calculated inrush current duration is 2.36 ms with 250-mA inrush current.

MOSFET BUK7Y4R8-60E having 60-V VDS and ±20-V VGS rating is selected for Q2. Power dissipation during inrush is well within the MOSFET safe operating area (SOA).