JAJSJD6A July   2021  – December 2021 TPS22992

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics (VBIAS = 5 V)
    6. 7.6  Electrical Characteristics (VBIAS = 3.3 V)
    7. 7.7  Electrical Characteristics (VBIAS = 1.5 V)
    8. 7.8  Switching Characteristics (VBIAS = 5 V)
    9. 7.9  Switching Characteristics (VBIAS = 3.3 V)
    10. 7.10 Switching Characteristics (VBIAS = 1.5 V)
    11. 7.11 Typical Characteristics
  8. 8 Timing Diagram
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 ON and OFF Control
      2. 9.3.2 Adjustable Quick Output Discharge
      3. 9.3.3 Adjustable Slew Rate
      4. 9.3.4 Power Good (PG) Signal
      5. 9.3.5 Thermal Shutdown
      6. 9.3.6 Short Circuit Protection (TPS22992S)
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Performance Plots
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 サポート・リソース
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

12.1 Layout Guidelines

For best performance, all traces must be as short as possible. To be most effective, the input and output capacitors must be placed close to the device to minimize the effects that parasitic trace inductances can have on normal operation. Using wide traces for VIN, VOUT, and GND helps minimize the parasitic electrical effects.