JAJSJE1A July   2021  – December 2021 TPS1HC100-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 説明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1. 5.1 Recommended Connections for Unused Pins
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SNS Timing Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Accurate Current Sense
      2. 8.3.2 Programmable Current Limit
        1. 8.3.2.1 Capacitive Charging
      3. 8.3.3 Inductive-Load Switching-Off Clamp
      4. 8.3.4 Full Protections and Diagnostics
        1. 8.3.4.1  Short-Circuit and Overload Protection
        2. 8.3.4.2  Open-Load and Short-to-Battery Detection
        3. 8.3.4.3  Short-to-Battery Detection
        4. 8.3.4.4  Reverse-Polarity and Battery Protection
        5. 8.3.4.5  Latch-Off Mode
        6. 8.3.4.6  Thermal Protection Behavior
        7. 8.3.4.7  UVLO Protection
        8. 8.3.4.8  Loss of GND Protection
        9. 8.3.4.9  Loss of Power Supply Protection
        10. 8.3.4.10 Reverse Current Protection
        11. 8.3.4.11 Protection for MCU I/Os
      5. 8.3.5 Diagnostic Enable Function
    4. 8.4 Device Functional Modes
      1. 8.4.1 Working Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Dynamically Changing Current Limit
        2. 9.2.2.2 AEC Q100-012 Test Grade A Certification
        3. 9.2.2.3 EMC Transient Disturbances Test
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
      1. 11.2.1 Without a GND Network
      2. 11.2.2 With a GND Network
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

8.3.4 Full Protections and Diagnostics

Table 8-1 is when DIAG_EN is enabled. When DIAG_EN is low, current sense and FLT are disabled. The output is in high-impedance mode. Refer to Table 8-1 for details.

Table 8-1 Diagnostic Enable Logic Table
DIAG_EN IN Condition Protections and Diagnostics
HIGH ON See Fault Table
OFF
LOW ON Diagnostics disabled, protection normal
SNS and FLT are high impedance
OFF
Table 8-2 Fault Table

Conditions

EN

VOUT

Latch

FLT

SNS

Behavior

Recovery

Normal

L

L

x

Hi-Z

0

 Normal

H

VBB – ILOAD × RON

x

Hi-Z

ILoad / Ksns

 Normal

Overcurrent

H

VBB – ILIM × RLOAD

x

L

VSNSFH

 Holds the current at the current limit until thermal shutdown or when the overcurrent event is removed. Typical deglitch time for device to recognize overcurrent fault and begin to act on it is 2.5 μs.

STG, Relative Thermal Shutdown, Absolute Thermal Shutdown

H

H/L

L

L

VSNSFH

 Shuts down when devices hits relative or absolute thermal shutdown. Typical deglitch time for device to recognize overcurrent fault and begin to act on it is 2.5 μs. Typical deglitch time for device to recognize a TABS fault is 20 μs.

Auto retries when THYS is met and it has been longer than tRETRY amount of time

H

H/L

H

L

VSNSFH

 Shuts down when devices hits relative or absolute thermal shutdown. Typical deglitch time for device to recognize overcurrent fault and begin to act on it is 2.5 μs. Typical deglitch time for device to recognize a TABS fault is 20 μs.

Stays off until latch or enable is toggled

Open load, STB

H

H

x

Hi-Z

ILoad / KSNS = ~0

 Normal behavior, user can judge through SNS pin output if it is an open load or not.

L

H

x

L

VSNSFH

 Internal pullup resistor is active. If VBB – VOUT < VOL then fault active. Typical deglitch time before fault is indicated is 700 μs.

Clears when fault goes away

Reverse Polarity

x

x

x

x

x

Channel turns on to lower power dissipation. Current into ground pin is limited by external ground network.
Table 8-3 Deglitch Time for Each Fault Condition

Fault Condition

Deglitch Time

ILIM

2.5 µs

TREL

2.5 µs

TABS

20 µs

Open load

700 µs