Layout is a critical portion of good power supply design. The following guidelines will help users design a PCB with the best power conversion performance, thermal performance, and minimized generation of unwanted EMI. For more detailed EMC design consideration and test report, please refer to the PCB Layout and Parameters Recommendation for TPS2583X EMC Performance application report.

1. Input capacitor: The input bypass capacitor C_IN must be placed as close as possible to the IN and PGND pins. Grounding for both the input and output capacitors should consist of localized top side planes that connect to the PGND pin and PAD. A combination of different values and packages of capacitors can help improve the EMC performance (for example: 10 μF + 0.1 μF + 2.2 nF). Besides, the distance between the input filter section and the output power section must be at least 15 mm to prevent the output high-frequency signal from coupling into the input filter. A 10-uF cap cross V_IN and PGND pin on top of SW is suggested for TPS2583x-Q1.
2. V_CC bypass capacitor: Place bypass capacitors for V_CC close to the VCC pin and ground the bypass capacitor to device ground.
3. Use a ground plane in one of the middle layers as noise shielding and heat dissipation path.
4. Connect the thermal pad to the ground plane. The QFN package has a thermal pad (PAD) connection that must be soldered down to the PCB ground plane. This pad acts as a heat-sink connection. The integrity of this solder connection has a direct bearing on the total effective R_θJA of the application.
5. Make V_IN, V_OUT and ground bus connections as wide as possible. This reduces any voltage drops on the input or output paths of the converter and maximizes efficiency.
6. Provide enough PCB area for proper heat sinking. As stated in the section, enough copper area must be used to ensure a low R_θJA, commensurate with the maximum load current and ambient temperature. Make the top and bottom PCB layers with two-ounce copper; and no less than one ounce. Use an array of heat-sinking vias to connect the thermal pad (PAD) to the ground plane on the bottom PCB layer. If the PCB design uses multiple copper layers (recommended), thermal vias can also be connected to the inner layer heat-spreading ground planes.
7. The SW pin connecting to the inductor should be as short as possible, and just wide enough to carry the load current without excessive heating. Short, thick traces or copper pours (shapes) will bring a high current conduction capacity to minimize parasitic resistance, but it will also cause a larger parasitic capacitance. Thus a balance should be found between smaller parasitic resistance and larger parasitic capacitance. And the current path should be kept straight forward to the inductor, otherwise the L-shaped or T-shaped path will make a sudden change of the impedance which causes signal reflection and impacts the performance of EMC. The output capacitors should be placed close to the V_OUT end of the inductor and closely grounded to PGND pin and exposed PAD. Besides, do not punch vias on SW lines. Using shielded inductors or molded inductors to reduce high-frequency radiation.
8. Sense and Set Resistors: The R_SNS and R_SET resistors connect to the current sense amplifier inputs at the CSP and CSN/OUT pins. For best current limit and cable compensation accuracy; short, parallel traces give the best performance. If it is not possible to place R_SNS and R_SET near the CSP and CSN/OUT pins, it is recommended that the traces from sense resistor be routed in parallel and of similar lengths. A small filter capacitor in parallel with R_SNS and a small filter capacitor from CSN/OUT to AGND help decouple noise.
9. R_ILIMIT and R_IMON resistors should be placed as close as possible to the ILIMIT and IMON pins and connected to AGND. If needed, these components can be placed on the bottom side of the PCB with signals routed through small vias.
10. Trace routing of DP_IN, DM_IN, DP_OUT, and DM_OUT: Route these traces as micro-strips with nominal differential impedance of 90 Ω. Minimize the use of vias in the high-speed data lines. Keep the reference GND plane devoid from cuts or splits above the differential pairs to prevent impedance discontinuities.
11. Keep the CC lines close to the same length. Do not create stubs or test points on the CC lines.
12. POL, LD_DET, FAULT and THERM_WARN (TPS25831-Q1) are open-drain outputs. They can be connected to the VCC pin via pull-up resistors. Suggested resistor value is 100 kΩ.
13. The area enclosed by current loop of input side and output side should be as small as possible; the area enclosed by the BOOT circuit should be as small as possible.
14. Power ground PGND and the signal ground AGND should be separated in the actual PCB layout.