The voltage on the EN/UVLO pin controls the ON or OFF operation of TPS2583xA-Q1. An EN/UVLO pin voltage higher than V_EN/UVLO-H is required to start the internal regulator and begin monitoring the CCn lines for a valid Type-C connection. The internal USB monitoring circuitry is on when V_IN is within the operation range and the EN/UVLO threshold is cleared; however, the buck regulator does not begin operation until a valid USB Type-C detection has been made. This feature ensures the "cold socket" (0 V) USB Type-C V_BUS requirement is met. The EN/UVLO pin is an input and cannot be left open or floating. The simplest way to enable the operation of the TPS2583xA-Q1 is to connect the EN to V_IN. This connection allows self-start-up of the TPS2583xA-Q1 when V_IN is within the operation range.

DP and DM data switch will also be turned on after the EN/UVLO pin set high.

Figure 10-2 Precision Enable Behavior

Many applications will benefit from the employment of an enable divider R_ENT and R_ENB (Figure 10-3) to establish a precision system UVLO level for the TPS2583xA. The system UVLO can be used for sequencing, ensuring reliable operation, or supply protection, such as a battery discharge level. To ensure the USB port V_BUS is within the 5-V operating range as required for USB compliance (for the latest USB specifications and requirements, refer to USB.org), TI suggest that the R_ENT and R_ENB resistors be chosen so that the TPS2583xA-Q1 enables when V_IN is approximately 6 V. Considering the drop out voltage of the buck regulator and IR loses in the system, 6 V provides adequate margin to maintain V_BUS within USB specifications. If system requirements such as a warm crank (start) automotive scenario require operation with V_IN < 6 V, the values of R_ENT and R_ENB can be calculated assuming a lower V_IN. An external logic signal can also be used to drive EN/UVLO input when a microcontroller is present and it is desirable to enable or disable the USB port remotely for other reasons.

Figure 10-3 System UVLO by Enable Divider

UVLO configuration using external resistors is governed by the following equations:

Equation 1.

Equation 2.

Example:

V_IN(ON) = 6 V (user choice)

R_ENB = 5 kΩ (user choice)

R_ENT = [(V_IN(ON) / V_{EN/UVLO_H}) –1] × R_ENB= 19.6 kΩ. Choose standard 20 kΩ.

Therefore V_IN(OFF) = 6 V × [1 – (0.09 V / 1.2 V)] = 5.55 V

A typical start-up waveform is shown in Figure 10-4, indicating typical timings when R_d connected to CC line. The rise time of DCDC VBUS voltage is about 5 ms.

Figure 10-4 Typical Start-Up Behavior, V_IN = 13.5 V, CC1 = R_d, R_IMON = 12.6 kΩ

For TPS2583xA-Q1, the pin voltage must meet the requirement below during 150 ms (typical) Rd assert deglitch time, see Figure 10-5:

• V_BUS < 0.8 V (typical), per Type-C requirement;
• V_{Dx_OUT} < 2.2 V (typical);
• V_{Dx_IN} < 1.5 V (typical);

After the TPS2583xA-Q1 Rd assert deglitch time, there is no additional requirement on these pins. In a real application, LD_DET pin can be used to configure the timing sequence.

Figure 10-5 TPS2583xA-Q1 Pin Voltage Requirement Under CDP/SDP Mode