JAJSJH8A
October 2020 – May 2021
DAC61402
,
DAC81402
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Device Comparison Table
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Timing Requirements: Write, IOVDD: 1.7 V to 2.7 V
7.7
Timing Requirements: Write, IOVDD: 2.7 V to 5.5 V
7.8
Timing Requirements: Read and Daisy Chain, FSDO = 0, IOVDD: 1.7 V to 2.7 V
7.9
Timing Requirements: Read and Daisy Chain, FSDO = 1, IOVDD: 1.7 V to 2.7 V
7.10
Timing Requirements: Read and Daisy Chain, FSDO = 0, IOVDD: 2.7 V to 5.5 V
7.11
Timing Requirements: Read and Daisy Chain, FSDO = 1, IOVDD: 2.7 V to 5.5 V
7.12
Timing Diagrams
7.13
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
R-2R Ladder DAC
8.3.2
Programmable-Gain Output Buffer
8.3.2.1
Sense Pins
8.3.3
DAC Register Structure
8.3.3.1
DAC Output Update
8.3.3.1.1
Synchronous Update
8.3.3.1.2
Asynchronous Update
8.3.3.2
Broadcast DAC Register
8.3.3.3
Clear DAC Operation
8.3.4
Internal Reference
8.3.5
Power-On Reset (POR)
8.3.5.1
Hardware Reset
8.3.5.2
Software Reset
8.3.6
Thermal Alarm
8.4
Device Functional Modes
8.4.1
Power-Down Mode
8.5
Programming
8.5.1
Stand-Alone Operation
8.5.2
Daisy-Chain Operation
8.5.3
Frame Error Checking
8.6
Register Map
8.6.1
NOP Register (address = 00h) [reset = 0000h]
8.6.2
DEVICEID Register (address = 01h) [reset = 0A70h or 0930h]
8.6.3
STATUS Register (address = 02h) [reset = 0000h]
8.6.4
SPICONFIG Register (address = 03h) [reset = 0AA4h]
8.6.5
GENCONFIG Register (address = 04h) [reset = 4000h]
8.6.6
BRDCONFIG Register (address = 05h) [reset = 000Fh]
8.6.7
SYNCCONFIG Register (address = 06h) [reset = 0000h]
8.6.8
DACPWDWN Register (address = 09h) [reset = FFFFh]
8.6.9
DACRANGE Register (address = 0Ah) [reset = 0000h]
8.6.10
TRIGGER Register (address = 0Eh) [reset = 0000h]
8.6.11
BRDCAST Register (address = 0Fh) [reset = 0000h]
8.6.12
DACn Register (address = 11h to 12h) [reset = 0000h]
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.3
Application Curves
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Documentation Support
12.1.1
Related Documentation
12.2
ドキュメントの更新通知を受け取る方法
12.3
サポート・リソース
12.4
Trademarks
12.5
静電気放電に関する注意事項
12.6
用語集
13
Mechanical, Packaging, and Orderable Information
1
特長
性能:
16 ビット分解能で単調性を規定
INL:16 ビット分解能で ±1LSB 以下
TUE:±0.05% FSR (最大値)
出力バッファを内蔵
フルスケール出力電圧:±5V、±10V、±20V、5V、10V、20V、40V
高い駆動能力:±15mA
チャネルごとのセンス・ピン
2.5V 高精度基準電圧を内蔵
初期精度:±2.5mV 以下
低ドリフト:10ppm/℃以下
高信頼性機能:
CRC エラー・チェック
短絡制限
障害ピン
50MHz、SPI 互換のシリアル・インターフェイス
4 線式モード、1.7V~5.5V での動作
リードバックおよびデイジーチェーン動作
温度範囲:-40℃~+125℃
パッケージ:5mm × 5mm、32 ピン QFN