at TA =
25°C, DVDD = 5.0 V, IOVDD = 1.8 V, internal reference enabled,
unipolar ranges: AVSS = 0 V and AVDD ≥ VMAX + 1.5 V for the
DAC range, bipolar ranges: AVSS ≤ VMIN − 1.5 V and AVDD ≥
VMAX + 1.5 V for the DAC range, and DAC outputs unloaded (unless otherwise
noted)
Figure 7-3 DAC81402 INL vs Digital Input Code
(Bipolar
Outputs) Figure 7-5 DAC81402 DNL vs Digital Input Code
(Bipolar
Outputs) Figure 7-7 DAC81402 TUE vs Digital Input Code
(Bipolar
Outputs) Figure 7-9 DAC61402 INL vs Digital Input Code
(Bipolar Outputs) Figure 7-11 DAC61402 DNL vs Digital Input Code
(Bipolar Outputs) Figure 7-13 DAC61402 TUE vs Digital Input Code
(Bipolar Outputs) Figure 7-15 DAC81402 INL vs Temperature Figure 7-17 DAC61402 INL vs Temperature Figure 7-19 TUE vs Temperature Figure 7-21 Unipolar Zero Code Error vs
Temperature Figure 7-23 Bipolar Zero Error vs
Temperature Figure 7-25 Full-Scale Error vs
Temperature Figure 7-27 Supply Current (AIDD,
AISS)
vs Digital Input Code Figure 7-29 Supply Current vs
Temperature Figure 7-31 Headroom and Footroom from Supply
vs Output Current Figure 7-33 Full-Scale Settling Time, Rising
Edge Figure 7-35 DAC Output Enable Glitch Figure 7-37 Glitch Impulse, 1 LSB Step,
Falling Edge Figure 7-39 Power-Down Response
DAC range: 0 V to 5 V,
midscale code |
Figure 7-41 DAC Output Noise Density vs
FrequencyFigure 7-43 Internal Reference Voltage vs
Temperature Figure 7-45 Internal Reference Voltage vs
Time Figure 7-47 Internal Reference Noise Figure 7-4 DAC81402 INL vs Digital Input Code
(Unipolar
Outputs) Figure 7-6 DAC81402 DNL vs Digital Input Code
(Unipolar
Outputs) Figure 7-8 DAC81402 TUE vs Digital Input Code
(Unipolar
Outputs) Figure 7-10 DAC61402 INL vs Digital Input Code
(Unipolar Outputs) Figure 7-12 DAC61402 DNL vs Digital Input Code
(Unipolar Outputs) Figure 7-14 DAC61402 TUE vs Digital Input Code
(Unipolar Outputs) Figure 7-16 DAC81402 DNL vs Temperature Figure 7-18 DAC61402 DNL vs Temperature Figure 7-20 Unipolar Offset Error vs
Temperature Figure 7-22 Bipolar Zero Code Error vs
Temperature Figure 7-24 Gain Error vs Temperature Figure 7-26 Supply Current (DIDD)
vs Digital Input Code Figure 7-28 Supply Current (IIOVDD)
vs Supply Voltage Figure 7-30 Power-Down Current vs
Temperature Figure 7-32 Source and Sink Capability Figure 7-34 Full-Scale Settling Time, Falling
Edge Figure 7-36 Glitch Impulse, 1 LSB Step,
Rising Edge Figure 7-38 Power-Up Response Figure 7-40 Clear Command Response
DAC range: 0 V to 5 V,
midscale code |
Figure 7-42 DAC Output NoiseFigure 7-44 Internal Reference Voltage
vs Supply Voltage Figure 7-46 Internal Reference Noise Density vs
Frequency Figure 7-48 Internal Reference Temperature Drift
Histogram