JAJSJH8A October   2020  – May 2021 DAC61402 , DAC81402

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements: Write, IOVDD: 1.7 V to 2.7 V
    7. 7.7  Timing Requirements: Write, IOVDD: 2.7 V to 5.5 V
    8. 7.8  Timing Requirements: Read and Daisy Chain, FSDO = 0, IOVDD: 1.7 V to 2.7 V
    9. 7.9  Timing Requirements: Read and Daisy Chain, FSDO = 1, IOVDD: 1.7 V to 2.7 V
    10. 7.10 Timing Requirements: Read and Daisy Chain, FSDO = 0, IOVDD: 2.7 V to 5.5 V
    11. 7.11 Timing Requirements: Read and Daisy Chain, FSDO = 1, IOVDD: 2.7 V to 5.5 V
    12. 7.12 Timing Diagrams
    13. 7.13 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 R-2R Ladder DAC
      2. 8.3.2 Programmable-Gain Output Buffer
        1. 8.3.2.1 Sense Pins
      3. 8.3.3 DAC Register Structure
        1. 8.3.3.1 DAC Output Update
          1. 8.3.3.1.1 Synchronous Update
          2. 8.3.3.1.2 Asynchronous Update
        2. 8.3.3.2 Broadcast DAC Register
        3. 8.3.3.3 Clear DAC Operation
      4. 8.3.4 Internal Reference
      5. 8.3.5 Power-On Reset (POR)
        1. 8.3.5.1 Hardware Reset
        2. 8.3.5.2 Software Reset
      6. 8.3.6 Thermal Alarm
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Mode
    5. 8.5 Programming
      1. 8.5.1 Stand-Alone Operation
      2. 8.5.2 Daisy-Chain Operation
      3. 8.5.3 Frame Error Checking
    6. 8.6 Register Map
      1. 8.6.1  NOP Register (address = 00h) [reset = 0000h]
      2. 8.6.2  DEVICEID Register (address = 01h) [reset = 0A70h or 0930h]
      3. 8.6.3  STATUS Register (address = 02h) [reset = 0000h]
      4. 8.6.4  SPICONFIG Register (address = 03h) [reset = 0AA4h]
      5. 8.6.5  GENCONFIG Register (address = 04h) [reset = 4000h]
      6. 8.6.6  BRDCONFIG Register (address = 05h) [reset = 000Fh]
      7. 8.6.7  SYNCCONFIG Register (address = 06h) [reset = 0000h]
      8. 8.6.8  DACPWDWN Register (address = 09h) [reset = FFFFh]
      9. 8.6.9  DACRANGE Register (address = 0Ah) [reset = 0000h]
      10. 8.6.10 TRIGGER Register (address = 0Eh) [reset = 0000h]
      11. 8.6.11 BRDCAST Register (address = 0Fh) [reset = 0000h]
      12. 8.6.12 DACn Register (address = 11h to 12h) [reset = 0000h]
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 用語集
  13. 13Mechanical, Packaging, and Orderable Information

9.2.2 Detailed Design Procedure

The DACx1402 are an excellent choice for this application because of their exceptional linearity and programmable output ranges which simplify the drive stage design. Since the maximum output voltage requirements is ±20 V, the AVDD and AVSS supplies should be set to 21 V and −21 V, respectively. In unipolar output range, the AVDD supply should be set to 41 V for a full-scale output voltage of 40 V. In unipolar designs, the AVSS supply can be tied to ground. In all cases, the supply voltages must be selected such that the AVDD − AVSS voltage does not exceed 41.5 V.

The analog output module design includes an external electrical overstress protection circuit for short circuit events. R_LIMIT sets the maximum current flowing into the device in the event of an electrical overstress condition. The design uses a compensation capacitor for driving large cables such as the ones found in industrial environments. A CCOMP value of 470 pF is sufficient to drive capacitive loads as large as 1 μF.

Figure 9-2 shows a simplified structure of the device output pins, represented as a pair of clamp-to-rail diodes connected to the AVDD and AVSS supply rails.

GUID-20200825-CA0I-TXG8-B3LZ-2MMSTQ4XPRW3-low.svg Figure 9-2 Electrical Overstress (EOS) Protection Scheme

If the device output pins are exposed to industrial transient testing without external protection components, the diode structures will become forward biased and conduct current. If the conducted current is large, as is common in high-voltage industrial transient tests, the structures will become permanently damaged and impact the device functionality.

Both attenuation and diversion strategies are implemented to protect the device. Attenuation is realized by the capacitor Cext which forms an RC low-pass filter when interacting with the source impedance of the transient generator. The ferrite bead FB1 also helps attenuate high-frequency currents, along with both AC and DC current limiters realized by the series pass elements R1, R2, and R3.

Diversion is achieved by the transient voltage suppressor (TVS) diode D3 and clamp-to-rail diodes D1 and D2. The combined effects of both strategies effectively limits the current flowing into the device internal diode structures to prevent permanent damage. If we assume the schottky diode clamps VOUT to ±1.5 V from rail, then the peak current entering the device is equal to 80 mA, assuming R1 = 10 Ω and the diode FB is 0.7 V. It is important to also include the TVS diodes D4 and D5 at the AVDD and AVSS nodes in order to provide a discharge path for the energy sent to these nodes through diodes D4, D5, and the internal diode structures. In the abscensce of these diodes when current is diverted to these nodes decoupling capacitors will charge, slowly increasing the voltage at these nodes which can exceed the threshold limits of AVDD and AVSS.