To ensure clean start-up, the TPS929240-Q1 uses UVLO and POR circuitry to clear its internal registers upon power up and to reset registers with its default values.

The TPS929240-Q1 has internal UVLO circuits so that when either input voltage V_(VBAT) or LDO output voltage V_(LDO) is lower than its UVLO threshold, POR is triggered. In POR state, the device resets digital core and all registers to default value. FLAG_POR and FLAG_ERR register are set to 1 for each POR cycle to indicate the POR history.

Before both powers are above UVLO thresholds, the TPS929240-Q1 stays in POR state with all outputs off and ERR pulled down. Once both power supplies are above UVLO threshold, the device enters INIT mode for initialization releasing ERR pulldown. A programmable timer starts counting in INIT state, the timer length can be set by EEPROM register INITTIMER. When the timer is completed, the device switches to NORMAL state. In INIT state, setting CLRPOR to 1 clears FLAG_POR, disables the timer, and sets the device to NORMAL state.

Upon powering up, the TPS929240-Q1 automatically loads all settings stored in EEPROM to correlated registers and sets the other registers to default value which don't have correlated EEPROM. All channels are powered up in OFF state by default to avoid unwanted blinking.

Writing 1 to REGDEFAULT manually loads EEPROM setting to the correlated registers and set the other registers to default value. After REGDEFAULT is set, the FLAG_POR is cleared to 0. Writing 1 to CLRPOR also resets the FLAG_POR register to 0. TI recommends setting REGDEFAULT to 1 to clear the internal registers every time after POR. The REGDEFAULT automatically resets to 0.