JAJSJT6A August   2020  – July 2021 TPS65994AD

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Recommended Capacitance
    5. 6.5  Thermal Information
    6. 6.6  Power Supply Characteristics
    7. 6.7  Power Consumption
    8. 6.8  PP_5V Power Switch Characteristics
    9. 6.9  PP_EXT Power Switch Characteristics
    10. 6.10 Power Path Supervisory
    11. 6.11 CC Cable Detection Parameters
    12. 6.12 CC VCONN Parameters
    13. 6.13 CC PHY Parameters
    14. 6.14 Thermal Shutdown Characteristics
    15. 6.15 ADC Characteristics
    16. 6.16 Input/Output (I/O) Characteristics
    17. 6.17 I2C Requirements and Characteristics
    18. 6.18 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  USB-PD Physical Layer
        1. 8.3.1.1 USB-PD Encoding and Signaling
        2. 8.3.1.2 USB-PD Bi-Phase Marked Coding
        3. 8.3.1.3 USB-PD Transmit (TX) and Receive (Rx) Masks
        4. 8.3.1.4 USB-PD BMC Transmitter
        5. 8.3.1.5 USB-PD BMC Receiver
        6. 8.3.1.6 Squelch Receiver
      2. 8.3.2  Power Management
        1. 8.3.2.1 Power-On And Supervisory Functions
        2. 8.3.2.2 VBUS LDO
      3. 8.3.3  Power Paths
        1. 8.3.3.1 Internal Sourcing Power Paths
          1. 8.3.3.1.1  PP_5Vx Current Clamping
          2. 8.3.3.1.2  PP_5Vx Local Overtemperature Shut Down (OTSD)
          3. 8.3.3.1.3  PP_5Vx Current Sense
          4. 8.3.3.1.4  PP_5Vx OVP
          5. 8.3.3.1.5  PP_5Vx UVLO
          6. 8.3.3.1.6  PP_5Vx Reverse Current Protection
          7. 8.3.3.1.7  Fast Role Swap
          8. 8.3.3.1.8  PP_CABLE Current Clamp
          9. 8.3.3.1.9  PP_CABLE Local Overtemperature Shut Down (OTSD)
          10. 8.3.3.1.10 PP_CABLE UVLO
        2. 8.3.3.2 Sink Path Control
          1. 8.3.3.2.1 Overvoltage Protection (OVP)
          2. 8.3.3.2.2 Reverse-Current Protection (RCP)
          3. 8.3.3.2.3 VBUS UVLO
          4. 8.3.3.2.4 Discharging VBUS to Safe Voltage
      4. 8.3.4  Cable Plug and Orientation Detection
        1. 8.3.4.1 Configured as a Source
        2. 8.3.4.2 Configured as a Sink
        3. 8.3.4.3 Configured as a DRP
        4. 8.3.4.4 Fast Role Swap Signal Detection
        5. 8.3.4.5 Dead Battery Advertisement
      5. 8.3.5  Default Behavior Configuration (ADCIN1, ADCIN2)
      6. 8.3.6  ADC
      7. 8.3.7  DisplayPort Hot-Plug Detect (HPD)
      8. 8.3.8  Digital Interfaces
        1. 8.3.8.1 General GPIO
        2. 8.3.8.2 I2C Interface
      9. 8.3.9  Digital Core
      10. 8.3.10 I2C Interface
        1. 8.3.10.1 I2C Interface Description
        2. 8.3.10.2 I2C Clock Stretching
        3. 8.3.10.3 I2C Address Setting
        4. 8.3.10.4 Unique Address Interface
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pin Strapping to Configure Default Behavior
      2. 8.4.2 Power States
      3. 8.4.3 Thermal Shutdown
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Type-C VBUS Design Considerations
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Type-C Connector VBUS Capacitors
          2. 9.2.1.2.2 VBUS Schottky and TVS Diodes
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Notebook Design Supporting PD Charging
        1. 9.2.2.1 USB and DisplayPort Notebook Supporting PD Charging
          1. 9.2.2.1.1 Design Requirements
          2. 9.2.2.1.2 Detailed Design Procedure
            1. 9.2.2.1.2.1 USB Power Delivery Source Capabilities
            2. 9.2.2.1.2.2 USB Power Delivery Sink Capabilities
            3. 9.2.2.1.2.3 USB and DisplayPort Supported Data Modes
            4. 9.2.2.1.2.4 TUSB1046 Super Speed Mux GPIO Control
        2. 9.2.2.2 Thunderbolt Notebook Supporting PD Charging
          1. 9.2.2.2.1 Design Requirements
          2. 9.2.2.2.2 Detailed Design Procedure
            1. 9.2.2.2.2.1 USB Power Delivery Source Capabilities
            2. 9.2.2.2.2.2 USB Power Delivery Sink Capabilities
            3. 9.2.2.2.2.3 Thunderbolt Supported Data Modes
            4. 9.2.2.2.2.4 I2C Design Requirements
            5. 9.2.2.2.2.5 TS3DS10224 SBU Mux for AUX and LSTX/RX
  10. 10Power Supply Recommendations
    1. 10.1 3.3-V Power
      1. 10.1.1 VIN_3V3 Input Switch
      2. 10.1.2 VBUS 3.3-V LDO
    2. 10.2 1.5-V Power
    3. 10.3 Recommended Supply Load Capacitance
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Top TPS65994AD Placement and Bottom Component Placement and Layout
    2. 11.2 Layout Example
    3. 11.3 Component Placement
    4. 11.4 Routing PP_5V, VBUS, VIN_3V3, LDO_3V3, LDO_1V5
    5. 11.5 Routing CC and GPIO
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Package Option Addendum
      1. 13.1.1 Tape and Reel Information

6.17 I2C Requirements and Characteristics

Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V (2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I2C_EC_IRQ , I2C2s_IRQ
OD_VOL_IRQ Low level output voltage IOL = 2 mA 0.4 V
OD_LKG_IRQ Leakage Current Output is Hi-Z, VI2Cx_IRQ = 3.45 V –1 1 µA
I2C3m_IRQ
IRQ_VIH High-Level input voltage VLDO_3V3 = 3.3V 1.3 V
IRQ_VIH_THRESH High-Level input voltage threshold VLDO_3V3 = 3.3V 0.72 1.3 V
IRQ_VIL low-level input voltage VLDO_3V3 = 3.3V 0.54 V
IRQ_VIL_THRESH low-level input voltage threshold VLDO_3V3 = 3.3V 0.54 1.08 V
IRQ_HYS input hysteresis voltage VLDO_3V3 = 3.3V 0.09 V
IRQ_DEG input deglitch 20 ns
IRQ_ILKG I2C3m_IRQ leakage current VI2C3m_IRQ = 3.45 V –1 1 µA
SDA and SCL Common Characteristics (Master, Slave)
VIL Input low signal VLDO_3V3=3.3V, 0.54 V
VIH Input high signal VLDO_3V3=3.3V,  1.3 V
VHYS Input hysteresis VLDO_3V3=3.3V 0.165 V
VOL Output low voltage IOL=3 mA 0.36 V
ILEAK Input leakage current Voltage on pin = VLDO_3V3 –3 3 µA
IOL Max output low current VOL=0.4 V 15 mA
IOL Max output low current VOL=0.6 V 20 mA
tf Fall time from 0.7*VDD to 0.3*VDD VDD = 1.8V, 10 pF ≤ Cb ≤ 400 pF 12 80 ns
VDD = 3.3V, 10 pF ≤ Cb ≤ 400 pF 12 150 ns
tSP I2C pulse width surpressed 50 ns
CI pin capacitance (internal) 10 pF
Cb Capacitive load for each bus line (external) 400 pF
tHD;DAT Serial data hold time VDD = 1.8V or 3.3V 0 ns
SDA and SCL Standard Mode Characteristics (Slave)
fSCLS Clock frequency VDD = 1.8V or 3.3V 100 kHz
tVD;DAT Valid data time Transmitting Data, VDD = 1.8V or 3.3V, SCL low to SDA output valid 3.45 µs
tVD;ACK Valid data time of ACK condition Transmitting Data, VDD = 1.8V or 3.3V, ACK signal from SCL low to SDA (out) low 3.45 µs
SDA and SCL Fast Mode Characteristics (Slave)
fSCLS Clock frequency VDD = 1.8V or 3.3V 100 400 kHz
tVD;DAT Valid data time Transmitting data, VDD = 1.8V, SCL low to SDA output valid 0.9 µs
tVD;ACK Valid data time of ACK condition Transmitting data, VDD = 1.8V or 3.3V, ACK signal from SCL low to SDA (out) low 0.9 µs
SDA and SCL Fast Mode Plus Characteristics (Slave)
fSCLS Clock frequency  (1) VDD = 1.8V or 3.3V, master controls SCL frequency such that: tLOW > tVD;ACK + tSU;DAT, TJ ≤ 65oC 400 1000 kHz
tVD;DAT Valid data time Transmitting data, VDD = 1.8V or 3.3V, SCL low to SDA output valid, TJ ≤ 65 oC 0.55 µs
tVD;ACK Valid data time of ACK condition Transmitting data, VDD = 1.8V or 3.3V, ACK signal from SCL low to SDA (out) low, TJ ≤ 65 oC 0.55 µs
SDA and SCL Fast Mode Characteristics (Master)
fSCLM Clock frequency for master(3) VDD = 3.3V(4) 400 410 kHz
VDD = 1.8V 390 400
tHD;STA Start or repeated start
condition hold time		 VDD = 3.3V 0.6 µs
tLOW Clock low time VDD = 3.3V 1.3     µs
tHIGH Clock high time VDD = 3.3V 0.6     µs
tSU;STA Start or repeated start
condition setup time		 VDD = 3.3V 0.6     µs
tSU;DAT Serial data setup time Transmitting data, VDD = 3.3V 100     ns
tSU;STO Stop condition setup time VDD = 3.3V 0.6   µs
tBUF Bus free time between stop and
start		 VDD = 3.3V 1.3     µs
tVD;DAT Valid data time Transmitting data, VDD = 3.3V, SCL low to SDA output valid   0.9 µs
tVD;ACK Valid data time of ACK condition Transmitting data, VDD = 3.3V, ACK signal from SCL low to SDA (out) low   0.9 µs
(1) Fast Mode Plus is only recommended during boot when the device is in PTCH mode.
(2) The master or slave connected to the device follows I2C specifications.
(3) Actual frequency is dependent upon bus capacitance and pull-up resistance.
(4) Measured at 400kHz with Rp=1kΩ and Cb=145pF