JAJSK58D January   2022  – April 2024 TPS4811-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Charge Pump and Gate Driver output (VS, PU, PD, BST, SRC)
      2. 8.3.2  Capacitive Load Driving
        1. 8.3.2.1 FET Gate Slew Rate Control
        2. 8.3.2.2 Using Precharge FET - (with TPS48111-Q1 Only)
      3. 8.3.3  Short-Circuit Protection
        1. 8.3.3.1 Overcurrent Protection With Auto-Retry
        2. 8.3.3.2 Overcurrent Protection With Latch-Off
      4. 8.3.4  Short-Circuit Protection
      5. 8.3.5  Analog Current Monitor Output (IMON)
      6. 8.3.6  Overvoltage (OV) and Undervoltage Protection (UVLO)
      7. 8.3.7  Device Functional Mode (Shutdown Mode)
      8. 8.3.8  Remote Temperature sensing and Protection (DIODE)
      9. 8.3.9  Output Reverse Polarity Protection
      10. 8.3.10 TPS4811x-Q1 as a Simple Gate Driver
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application: Driving HVAC PTC Heater Load on KL40 Line in Power Distribution Unit
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Typical Application: Driving B2B FETs With Pre-charging the Output Capacitance
      1. 9.3.1 Design Requirements
      2. 9.3.2 External Component Selection
      3. 9.3.3 Application Curves
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 ドキュメントの更新通知を受け取る方法
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 静電気放電に関する注意事項
    5. 10.5 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

9.3.2 External Component Selection

By following similar design procedure as outlined in Detailed Design Procedure, the external component values are calculated as below:

  • RSNS = 500 μΩ

  • RSET = 100 Ω

  • RIWRN = 47 kΩ to set 50 A as overcurrent protection threshold

  • RISCP = 1.4 kΩ to set 60 A as short-circuit protection threshold

  • CTMR = 68 nF to set 1 ms circuit breaker time

  • R1 and R2 are selected as 470 kΩ and 24.9 kΩ respectively to set VIN undervoltage lockout threshold at 24 V

  • RIMON = 15 kΩ to limit maximum V(IMON) voltage to 3.3 V at full-load current of 50 A

  • To reduce conduction losses, IAUS300N08S5N012 MOSFET is selected. Two FETs are used in parallel for control and another two FETs are used in parallel for reverse current blocking

    • 80-V VDS(MAX) and ±20-V VGS(MAX)

    • RDS(ON) is 1-mΩ typical at 10-V VGS

    • Qg of each MOSFET is 231 nC

  • CBST = (4 × Qg) / 1 V = 1 μF

Selection of Pre-Charge Resistor

The value of pre-charge resistor must be selected to limit the inrush current to Iinrush as per Equation 23.

Equation 23. TPS4811-Q1

The power rating of the pre-charge resistor is decided by the average power dissipation given by Equation 24.

Equation 24. TPS4811-Q1

The peak power dissipation in the pre-charge resistor is given by Equation 25.

Equation 25. TPS4811-Q1

Two 220-Ω, 1.5-W, 5% CRCW2512220RJNEGHP resistors are used in parallel to support both average and peak power dissipation.

TI suggests the designer to share the entire power dissipation profile of pre-charge resistor with the resistor manufacturer and get their recommendation.