JAJSK72A june   2020  – october 2020 UCC23514

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Function
    1.     Pin Functions for UCC23514E
    2.     Pin Functions for UCC23514M
    3.     Pin Functions for UCC23514S
    4.     Pin Functions for UCC23514V
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristics
    12. 6.12 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Propagation Delay, rise time and fall time
    2. 7.2 IOH and IOL testing
    3. 7.3 CMTI Testing
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Supply
      2. 8.3.2 Input Stage
      3. 8.3.3 Output Stage
      4. 8.3.4 Protection Features
        1. 8.3.4.1 Undervoltage Lockout (UVLO)
        2. 8.3.4.2 Active Pulldown
        3. 8.3.4.3 Short-Circuit Clamping
        4. 8.3.4.4 Active Miller Clamp (UCC23514M)
    4. 8.4 Device Functional Modes
      1. 8.4.1 ESD Structure
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Selecting the Input Resistor
        2. 9.2.2.2 Gate-Driver Output Resistor
        3. 9.2.2.3 Estimate Gate-Driver Power Loss
        4. 9.2.2.4 Estimating Junction Temperature
        5. 9.2.2.5 Selecting VCC Capacitor
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 PCB Material
  13. 12Mechanical, Packaging, and Orderable Information

9.2.2.2 Gate-Driver Output Resistor

The external gate-driver resistors, RG(ON) and RG(OFF) are used to:

  1. Limit ringing caused by parasitic inductances and capacitances
  2. Limit ringing caused by high voltage or high current switching dv/dt, di/dt, and body-diode reverse recovery
  3. Fine-tune gate drive strength, specifically peak sink and source current to optimize the switching loss
  4. Reduce electromagnetic interference (EMI)

The output stage has a pull up structure consisting of a P-channel MOSFET and an N-channel MOSFET in parallel. The combined peak source current is 4.5 A Use Equation 1 to estimate the peak source current as an example.

Equation 1. GUID-85DD1DB1-1C5F-4DE4-896A-55278D7B347C-low.gif

where

  • RGON is the external turnon resistance.
  • RGFET_Int is the power transistor internal gate resistance, found in the power transistor data sheet. We will assume 0Ω for our example
  • IOH is the peak source current which is the minimum value between 4.5A, the gate-driver peak source current, and the calculated value based on the gate-drive loop resistance.
  • VGDF is the forward voltage drop for each of the diodes in series with RGON and RGOFF. The diode drop for this example is 0.7 V.

In this example, the peak source current is approximately 1.7A as calculated in Equation 2.

Equation 2. GUID-1B3DEC8C-F502-43CE-BFB3-9C9A4054CCBD-low.gif

Similarly, use Equation 3 to calculate the peak sink current.

Equation 3. GUID-2CB01417-A385-46A5-8427-F942C0C2363E-low.gif

where

  • RGOFF is the external turnoff resistance.
  • IOL is the peak sink current which is the minimum value between 5.3A, the gate-driver peak sink current, and the calculated value based on the gate-drive loop resistance.

In this example, the peak sink current is the minimum of Equation 4 and 5.3A.

Equation 4. GUID-C20A7CAD-A8C8-41B0-B0B8-67A28D2D5288-low.gif

The diodes shown in series with each, RGON and RGOFF, in Figure 9-1, Figure 9-2, and Figure 9-4 ensure the gate drive current flows through the intended path, respectively, during turn-on and turn-off. Note that the diode forward drop will reduce the voltage level at the gate of the power switch. To achieve rail-to-rail gate voltage levels, add a resistor from the VOUT pin to the power switch gate, with a resistance value approximately 20 times higher than RGON and RGOFF. For the examples described in this section, a good choice is 100 Ω to 200 Ω.

The UCC23514S provides split output pins, OUTH and OUTL, which provide separate paths for turn-on and turn-off current. The series diodes are not necessary when this device option is used, as shown in Figure 9-3. For this case, substitute VGDF = 0 V in the equations above. The UCC23514S provides rail-to-rail gate voltage levels without need for additional parallel resistors.

Note:

The estimated peak current is also influenced by PCB layout and load capacitance. Parasitic inductance in the gate-driver loop can slow down the peak gate-drive current and introduce overshoot and undershoot. Therefore, TI strongly recommends that the gate-driver loop should be minimized. Conversely, the peak source and sink current is dominated by loop parasitics when the load capacitance (CISS) of the power transistor is very small (typically less than 1 nF) because the rising and falling time is too small and close to the parasitic ringing period.