JAJSKA0A march   2020  – november 2020 BQ25306

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 概要 (続き)
  7. 6 Device Comparison Table
  8. 7 Pin Configuration and Functions
  9. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Device Power Up
        1. 9.3.1.1 Power-On-Reset (POR)
        2. 9.3.1.2 REGN Regulator Power Up
        3. 9.3.1.3 Charger Power Up
        4. 9.3.1.4 Charger Enable and Disable by EN Pin
        5. 9.3.1.5 Device Unplugged from Input Source
      2. 9.3.2 Battery Charging Management
        1. 9.3.2.1 Battery Charging Profile
        2. 9.3.2.2 Precharge
        3. 9.3.2.3 Charging Termination
        4. 9.3.2.4 Battery Recharge
        5. 9.3.2.5 Charging Safety Timer
        6. 9.3.2.6 Thermistor Temperature Monitoring
      3. 9.3.3 Charging Status Indicator (STAT)
      4. 9.3.4 Protections
        1. 9.3.4.1 Voltage and Current Monitoring
          1. 9.3.4.1.1 Input Over-Voltage Protection
          2. 9.3.4.1.2 Input Voltage Dynamic Power Management (VINDPM)
          3. 9.3.4.1.3 Input Current Limit
          4. 9.3.4.1.4 Cycle-by-Cycle Current Limit
        2. 9.3.4.2 Thermal Regulation and Thermal Shutdown
        3. 9.3.4.3 Battery Protection
          1. 9.3.4.3.1 Battery Over-Voltage Protection (VBAT_OVP)
          2. 9.3.4.3.2 Battery Short Circuit Protection
        4. 9.3.4.4 ICHG Pin Open and Short Protection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Disable Mode, HiZ Mode, Sleep Mode, Charge Mode, Termination Mode, and Fault Mode
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Typical Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Charge Voltage Settings
          2. 10.2.1.2.2 Charge Current Setting
          3. 10.2.1.2.3 Inductor Selection
          4. 10.2.1.2.4 Input Capacitor
          5. 10.2.1.2.5 Output Capacitor
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Typical Application with External Power Path
        1. 10.2.2.1 Design Requirements
      3. 10.2.3 Typical Application with MCU Programmable Charge Current
        1. 10.2.3.1 Design Requirements
  12. 11Power Supply Recommendations
  13. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 サード・パーティ製品に関する免責事項
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 サポート・リソース
    5. 13.5 Trademarks
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 用語集
  15. 14Mechanical, Packaging, and Orderable Information

8.7 Typical Characteristics

GUID-20201112-CA0I-RLNW-2PVN-PZFJPDCPV8NK-low.svg
fSW = 1.2 MHz Inductance = 1.0 uH
VVBUS = 5.0 V, VBAT = 3.8 V Inductor DCR = 10 mΩ
Figure 8-1 1-Cell Battery Charge Efficiency vs. Charge Current
GUID-20201102-CA0I-Z5WR-9HC7-WFD4GKWCJXSJ-low.svg
fSW = 1.2 MHz Inductance = 2.2 uH
VBAT = 7.6 V Inductor DCR = 20 mΩ
Figure 8-3 2-Cell Battery Charge Efficiency vs. Charge Current
GUID-20201112-CA0I-8J97-L1LH-9MFSR0PSKPGX-low.svgFigure 8-5 Termination Current as Percentage of Charge Current vs. Charge Current (1-cell)
GUID-20201112-CA0I-WXNH-WKBM-HQ5GBVK2HB0X-low.svgFigure 8-7 KICHG vs. Charge Current
GUID-20201009-CA0I-LTXN-6Z3X-8SB6DZ89399W-low.svg
fSW = 1.2 MHz Inductance = 2.2 uH
VBAT = 3.8 V Inductor DCR = 20 mΩ
Figure 8-2 1-Cell Battery Charge Efficiency vs. Charge Current
GUID-20200918-CA0I-JBNL-S8MK-FGDQVGZ1M92L-low.gifFigure 8-4 VINDPM vs. Junction Temperature
GUID-20201112-CA0I-2TF4-DM0H-HWSG5GPN9QF2-low.svgFigure 8-6 Termination Current as Percentage of Charge Current vs. Charge Current (2-cell)
GUID-20201112-CA0I-FHF7-GRZC-P6CFB4BMTMQW-low.svgFigure 8-8 Charge Current vs. Charge Current Setting Resistance RICHG