JAJSKP0B february   2022  – june 2023 TIOS102 , TIOS1023 , TIOS1025

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 ESD Ratings - IEC Specifications
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1  Current Limit Configuration
      2. 8.3.2  Current Fault Detection, Indication and Auto Recovery
      3. 8.3.3  Thermal Warning, Thermal Shutdown
      4. 8.3.4  Fault Reporting (NFAULT)
      5. 8.3.5  Device Function Tables
      6. 8.3.6  The Integrated Voltage Regulator (LDO)
      7. 8.3.7  Reverse Polarity Protection
      8. 8.3.8  Integrated Surge Protection and Transient Waveform Tolerance
      9. 8.3.9  Power Up Sequence
      10. 8.3.10 Undervoltage Lock-Out (UVLO)
    4. 8.4 Device Functional Modes
      1. 8.4.1 NPN Configuration (N-Switch Mode)
      2. 8.4.2 PNP Configuration (P-Switch Mode)
      3. 8.4.3 Push-Pull Mode
  10. 9 Application Information Disclaimer
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 最大接合部温度チェック
        2. 9.2.2.2 Driving Capacitive Loads
        3. 9.2.2.3 Driving Inductive Loads
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 ドキュメントの更新通知を受け取る方法
    2. 12.2 サポート・リソース
    3. 12.3 Trademarks
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 用語集
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Mechanical Data

8.3.6 The Integrated Voltage Regulator (LDO)

The TIOS1023 and TIOS1025 each have an integrated linear voltage regulator (LDO) which can supply power to external components. The voltage regulator is specified for VCC voltages in the range of 7 V to 36 V (TIOS1025) or in the range of 5 V to 36 V (TIOS102, TIOS1023) with respect to GND. The LDO is capable of delivering up to 20 mA. The LDO output is current limited to 35-mA to limit the inrush current onto VCC_OUT decoupling capacitors during initial power up.

In the DSBGA (YAH) package, TIOS1023L offers pin-configurable LDO output via VSEL pin. When VSEL is connected to GND, VCC_OUT is configured to provide a 5-V output. When VSEL is left floating, VCC_OUT provides a 3.3-V output.

Table 8-4 LDO Output Configuration via VSEL pin (YAH Package)

VSEL pin connection

VCC_OUT

GND

5 V

Floating

3.3 V

The LDO is designed to be stable with standard ceramic capacitors with values of 1 μF or larger at the output. X5R- and X7R-type capacitors are best because they have minimal variation in value and ESR over temperature. Maximum ESR should be less than 1 Ω. With tolerance and dc bias effects, the minimum capacitance to ensure stability is 1 μF.