JAJSKR8B October   2019  – March 2022 TCAN1144-Q1 , TCAN1145-Q1 , TCAN1146-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  ESD Ratings
    4. 8.4  Recommended Operating Conditions
    5. 8.5  Thermal Information
    6. 8.6  Supply Characteristics
    7. 8.7  Electrical Characteristics
    8. 8.8  Timing Requirements
    9. 8.9  Switching Characteristics
    10. 8.10 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1  VSUP Pin
      2. 10.3.2  VIO Pin
      3. 10.3.3  VCC Pin
      4. 10.3.4  GND
      5. 10.3.5  INH/LIMP Pin
      6. 10.3.6  WAKE Pin
      7. 10.3.7  TXD Pin
      8. 10.3.8  RXD Pin
      9. 10.3.9  SDO/nINT Interrupt Pin
      10. 10.3.10 nCS Pin
      11. 10.3.11 SCLK
      12. 10.3.12 SDI
      13. 10.3.13 CANH and CANL Bus Pins
    4. 10.4 Device Functional Modes
      1. 10.4.1 Normal Mode
      2. 10.4.2 Standby Mode
      3. 10.4.3 Listen Only Mode
      4. 10.4.4 Sleep Mode
        1. 10.4.4.1 Bus Wake via RXD Request (BWRR) in Sleep Mode
        2. 10.4.4.2 Local Wake Up (LWU) via WAKE Input Terminal
      5. 10.4.5 Selective Wake-up
        1. 10.4.5.1 Selective Wake Mode (TCAN1145-Q1 and TCAN1146-Q1)
        2. 10.4.5.2 Frame Detection (TCAN1145-Q1 and TCAN1146-Q1)
        3. 10.4.5.3 Wake-Up Frame (WUF) Validation (TCAN1145-Q1 and TCAN1146-Q1)
        4. 10.4.5.4 WUF ID Validation (TCAN1145-Q1 and TCAN1146-Q1)
        5. 10.4.5.5 WUF DLC Validation (TCAN1145-Q1 and TCAN1146-Q1)
        6. 10.4.5.6 WUF Data Validation (TCAN1145-Q1 and TCAN1146-Q1)
        7. 10.4.5.7 Frame error counter (TCAN1145-Q1 and TCAN1146-Q1)
        8. 10.4.5.8 CAN FD Frame Tolerance (TCAN1145-Q1 and TCAN1146-Q1)
      6. 10.4.6 Fail-safe Features
        1. 10.4.6.1 Sleep Mode via Sleep Wake Error
        2. 10.4.6.2 Fail-safe Mode
      7. 10.4.7 Protection Features
        1. 10.4.7.1 Driver and Receiver Function
        2. 10.4.7.2 Floating Terminals
        3. 10.4.7.3 TXD Dominant Time Out (DTO)
        4. 10.4.7.4 CAN Bus Short Circuit Current Limiting
        5. 10.4.7.5 Thermal Shutdown
        6. 10.4.7.6 Under-Voltage Lockout (UVLO) and Unpowered Device
          1. 10.4.7.6.1 UVSUP, UVCC
          2. 10.4.7.6.2 UVIO
            1. 10.4.7.6.2.1 Fault Behavior
        7. 10.4.7.7 Watchdog (TCAN1144-Q1 and TCAN1146-Q1)
          1. 10.4.7.7.1 Watchdog Error Counter
          2. 10.4.7.7.2 Watchdog SPI Control Programming
          3. 10.4.7.7.3 Watchdog Timing
          4. 10.4.7.7.4 Question and Answer Watchdog
            1. 10.4.7.7.4.1 WD Question and Answer Basic information
            2. 10.4.7.7.4.2 Question and Answer Register and Settings
            3. 10.4.7.7.4.3 WD Question and Answer Value Generation
          5. 10.4.7.7.5 Question and Answer WD Example
            1. 10.4.7.7.5.1 Example configuration for desired behavior
            2. 10.4.7.7.5.2 Example of performing a question and answer sequence
      8. 10.4.8 Bus Fault Detection and Communication (TCAN1144-Q1 and TCAN1146-Q1)
      9. 10.4.9 SPI Communication
        1. 10.4.9.1 Chip Select Not (nCS):
        2. 10.4.9.2 SPI Clock Input (SCLK):
        3. 10.4.9.3 SPI Serial Data Input (SDI):
        4. 10.4.9.4 SPI Serial Data Output (SDO):
    5. 10.5 Programming
    6. 10.6 Register Maps
      1. 10.6.1  DEVICE_ID_y Register (Address = 0h + formula) [reset = value]
      2. 10.6.2  REV_ID_MAJOR Register (Address = 8h) [reset = 01h]
      3. 10.6.3  REV_ID_MINOR Register (Address = 9h) [reset = 00h]
      4. 10.6.4  SPI_RSVD_x Register (Address = Ah + formula) [reset = 00h]
      5. 10.6.5  Scratch_Pad_SPI Register (Address = Fh) [reset = 00h]
      6. 10.6.6  MODE_CNTRL Register (Address = 10h) [reset = 04h]
      7. 10.6.7  WAKE_PIN_CONFIG Register (Address = 11h) [reset = 4h]
      8. 10.6.8  PIN_CONFIG Register (Address = 12h) [reset = 00h]
      9. 10.6.9  WD_CONFIG_1 Register (Address = 13h) [reset = 15h]
      10. 10.6.10 WD_CONFIG_2 Register (Address = 14h) [reset = 02h]
      11. 10.6.11 WD_INPUT_TRIG Register (Address = 15h) [reset = 00h]
      12. 10.6.12 WD_RST_PULSE Register (Address = 16h) [reset = 07h]
      13. 10.6.13 FSM_CONFIG Register (Address = 17h) [reset = 00h]
      14. 10.6.14 FSM_CNTR Register (Address = 18h) [reset = 00h]
      15. 10.6.15 DEVICE_RST Register (Address = 19h) [reset = 00h]
      16. 10.6.16 DEVICE_CONFIG1 Register (Address = 1Ah) [reset = 00h]
      17. 10.6.17 DEVICE_CONFIG2 Register (Address = 1Bh) [reset = 0h]
      18. 10.6.18 SWE_DIS Register (Address 1Ch) [reset = 04h]
      19. 10.6.19 SDO_CONFIG Register (Address = 29h) [reset = 00h]
      20. 10.6.20 WD_QA_CONFIG Register (Address = 2Dh) [reset = 00h]
      21. 10.6.21 WD_QA_ANSWER Register (Address = 2Eh) [reset = 00h]
      22. 10.6.22 WD_QA_QUESTION Register (Address = 2Fh) [reset = 00h]
      23. 10.6.23 SW_ID1 Register (Address = 30h) [reset = 00h]
      24. 10.6.24 SW_ID2 Register (Address = 31h) [reset = 00h]
      25. 10.6.25 SW_ID3 Register (Address = 32h) [reset = 00h]
      26. 10.6.26 SW_ID4 Register (Address = 33h) [reset = 00h]
      27. 10.6.27 SW_ID_MASK1 Register (Address = 34h) [reset = 00h]
      28. 10.6.28 SW_ID_MASK2 Register (Address = 35h) [reset = 00h]
      29. 10.6.29 SW_ID_MASK3 Register (Address = 36h) [reset = 00h]
      30. 10.6.30 SW_ID_MASK4 Register (Address = 37h) [reset = 00h]
      31. 10.6.31 SW_ID_MASK_DLC Register (Address = 38h) [reset = 00h]
      32. 10.6.32 DATA_y Register (Address = 39h + formula) [reset = 00h]
      33. 10.6.33 SW_RSVD_y Register (Address = 41h + formula) [reset = 00h]
      34. 10.6.34 SW_CONFIG_1 Register (Address = 44h) [reset = 50h]
      35. 10.6.35 SW_CONFIG_2 Register (Address = 45h) [reset = 00h]
      36. 10.6.36 SW_CONFIG_3 Register (Address = 46h) [reset = 1Fh]
      37. 10.6.37 SW_CONFIG_4 Register (Address = 47h) [reset = 00h]
      38. 10.6.38 SW_CONFIG_RSVD_y Register (Address = 48h + formula) [reset = 00h]
      39. 10.6.39 INT_GLOBAL Register (Address = 50h) [reset = 00h]
      40. 10.6.40 INT_1 Register (Address = 51h) [reset = 00h]
      41. 10.6.41 INT_2 Register (Address = 52h) [reset = 40h]
      42. 10.6.42 INT_3 Register (Address 53h) [reset = 00h]
      43. 10.6.43 INT_CANBUS Register (Address = 54h) [reset = 00h]
      44. 10.6.44 INT_GLOBAL_ENABLE (Address = 55h) [reset = 00h]
      45. 10.6.45 INT_ENABLE_1 Register (Address = 56h) [reset = FFh]
      46. 10.6.46 INT_ENABLE_2 Register (Address = 57h) [reset = 1Fh]
      47. 10.6.47 INT_ENABLE_3 Register (Address = 58h) [reset = 0h]
      48. 10.6.48 INT_ENABLE_CANBUS Register (Address = 59h) [reset = 7Fh]
      49. 10.6.49 INT_RSVD_y Register (Address = 5Ah + formula) [reset = 00h]
  11. 11Application Information Disclaimer
    1. 11.1 Application Information
      1. 11.1.1 BUS Loading, Length and Number of Nodes
      2. 11.1.2 CAN Termination
        1. 11.1.2.1 Termination
        2. 11.1.2.2 CAN Bus Biasing
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1 Brownout
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Documentation Support
      1. 14.1.1 CAN Transceiver Physical Layer Standards:
      2. 14.1.2 EMC Requirements:
      3. 14.1.3 Conformance Test Requirements:
      4. 14.1.4 Related Documentation
    2. 14.2 Receiving Notification of Documentation Updates
    3. 14.3 サポート・リソース
    4. 14.4 Trademarks
    5. 14.5 Electrostatic Discharge Caution
    6. 14.6 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

10.4.9.4 SPI Serial Data Output (SDO):

This pin is high impedance until the SPI output is enabled via nCS. Once the SPI is enabled by a low on nCS, the SDO is immediately driven high or low showing the global interrupt register 8'h50, bit 7. The Global Interrupt register, INT_GLOBAL, is the first byte to be shifted out. The SDO pin provides data out from the device to the processor. For a write command this is the only data that will be provided on the SDO pin. For a read command the one to three bytes of data from successive address will be provided on the SDO line. Figure 10-38 and Figure 10-39 shows examples of a single address read and of a three sequential address read utilizing the 32-bit burst read. The 32-bit burst read shows the global interrupt register followed by the three requested data bytes.

GUID-D0EFB686-C54C-43E4-AD96-1B1C91EA1536-low.gifFigure 10-38 SPI Read
GUID-20200707-SS0I-3C0X-BMR2-THG7VN6HXWC7-low.gifFigure 10-39 32-bit SPI Burst Read.

Example on how to read three bytes of data from one SPI read command.

Note:

If a read happens faster than 2 µs after a write the global fault flag status may not reflect any status change that the write may have initiated.