Make sure that the connection to the VDD pin is low impedance. Good analog design practice recommends placing a minimum 0.1 µF ceramic capacitor as near as possible to the VDD pin. If a capacitor is not connected to the CT pin (TLV841C), then minimize parasitic capacitance on this pin so the rest time delay is not adversely affected.

• Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a greater than 0.1 µF ceramic capacitor as near as possible to the VDD pin.
• If a C_{CT_EXT} capacitor is used (TLV841C), place the capacitor as close as possible to the CT pin. If the CT pin is left unconnected, make sure to minimize the amount of parasitic capacitance on the pin to less than 5 pF.
• If a SENSE capacitor (C_SENSE) is used (TLV841S), place the capacitor as close as possible to the SENSE pin to further improve the noise immunity on the SENSE pin. Placing a 10 nF to 100 nF capacitor between the SENSE pin and GND can reduce the sensitivity to sensitivity to transient voltages on the monitored signal.
• Place the pull-up resistors on RESET pin as close to the pin as possible.