JAJSKU3D April   2020  – January 2023 TLV841

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (VDD)
        1. 8.3.1.1 VDD Hysteresis
        2. 8.3.1.2 VDD Transient Immunity
      2. 8.3.2 SENSE Input (TLV841S)
        1. 8.3.2.1 SENSE Hysteresis
        2. 8.3.2.2 Immunity to SENSE Pin Voltage Transients
      3. 8.3.3 User-Programmable Reset Time Delay for TLV841C only
      4. 8.3.4 Manual Reset (MR) Input for TLV841M only
      5. 8.3.5 Output Logic
        1. 8.3.5.1 RESET Output, Active-Low
        2. 8.3.5.2 RESET Output, Active-High
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD > VPOR)
      2. 8.4.2 Below Power-On-Reset (VDD < VPOR)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves: TLV841EVM
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 用語集
  13. 13Mechanical, Packaging, and Orderable Information

8.3.5.1 RESET Output, Active-Low

RESET (Active-Low) applies to TLV841xxDL (Open-Drain) and TLV841xxPL (Push-Pull) hence the "L" in the device name. RESET remains high (deasserted) as long as VDD/SENSE is above the negative threshold (VIT-) and the MR pin is floating or above VMR_H. If VDD/SENSE falls below the negative threshold (VIT-) or if MR is driven low, then RESET is asserted.

When MR is again logic high or floating and VDD/SENSE rise above VIT+ (VIT- + VHYS), the delay circuit will hold RESET low for the specified reset time delay (tD). When the reset time delay has elapsed, the RESET pin goes back to logic high voltage VOH.

The TLV841xxDL (Open-Drain) version, denoted with "D" in the device name, requires an external pull-up resistor to hold RESET pin high. Connect the external pull-up resistor to the desired pull-up voltage source and RESET can be pulled up to any voltage up to 5.5 V independent of the VDD voltage. To ensure proper voltage levels, give some consideration when choosing the external pull-up resistor values. The external pull-up resistor value determines the actual VOL, the output capacitive loading, and the output leakage current (Ilkg(OD)).

The Push-Pull variant (TLV841xxPL), denoted with "P" in the device name, does not require an external pull-up resistor