JAJSKU3 データシート

JAJSKU3D April 2020 – January 2023 TLV841

PRODUCTION DATA

7.6 Timing Requirements

At V_DDMIN ≤ V_DD ≤ 5.5 V, CT = MR = Open, RESET pull-up resistor R_pull-up = 100 kΩ to VDD, output load is C_LOAD = 10 pF and over the operating free-air temperature range –40°C to 125°C, unless otherwise noted. Typical values are at T_A = 25°C

PARAMETER		TEST CONDITIONS	TYP	MAX	UNIT
t_{P_HL}	Propagation detect delay for V_DD falling below V_IT–	V_DD= (V_IT++ 10%) to (V_IT– – 10%) ⁽²⁾	30	50	µs
t_D	Reset time delay (TLV841C variant)	CT pin = Open or NC	40	80	µs
		CT pin = 10 nF	6.2		ms
		CT pin = 1 µF	619		ms
t_D	Reset time delay (TLV841S and TLV841M variant) ⁽⁵⁾	Variant A ⁽³⁾	40	80	µs
		Variant B ⁽³⁾	2		ms
		Variant C ⁽³⁾	10		ms
		Variant D ⁽³⁾	30		ms
		Variant E ⁽³⁾	50		ms
		Variant F ⁽³⁾	80		ms
		Variant G ⁽³⁾	100		ms
		Variant H ⁽³⁾	150		ms
		Variant I ⁽³⁾	200		ms
t_{GI_VIT–}	Glitch immunity V_IT–	5% V_IT– overdrive ⁽⁴⁾	10		µs
t_STRT	Startup Delay ⁽¹⁾			300	µs
t_{MR_RES}	Propagation delay from MR low to reset	V_DD = 3.3 V, MR < V_{MR_L}	t_{P_HL}		µs
t_{MR_tD}	Delay from release MR to deassert reset	V_DD = 3.3 V, MR = V_{MR_L}to V_{MR_H}	t_D		ms
t_{MR_PW}	Glitch immunity MR pin		10		µs

(1) When VDD starts from less than the specified minimum V_DD and then exceeds V_POR, reset is release after the startup delay (t_STRT). For TLV841C variants a capacitor at CT pin will add t_D delay to t_STRT time

(2) t_{P_HL} measured from threhold trip point (V_IT–) to V_OL for active low variants and V_OH for active high variants.

(3) Refer device nomenclature table for variant description. V_DD transition from V_IT– – 10% to V_IT+ + 10% for TLV841M and TLV841C; V_SENSE transition from V_IT– – 10% to V_IT++ 10% for TLV841S

(4) Overdrive % = [(V_DD/ V_IT–) – 1] × 100% for TLV841M and TLV841C; Overdrive % = [(V_SENSE/ V_IT–) – 1] × 100% for TLV841S

(5) Specified by design and characterization