JAJSKV6D August   2020  – April 2024 DRV8714-Q1 , DRV8718-Q1

PRODMIX  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
    1. 5.1 VQFN (RVJ) 56-Pin Package and Pin Functions
    2. 5.2 VQFN (RHA) 40-Pin Package and Pin Functions
    3. 5.3 HTQFP (PHP) 48-Pin Package and Pin Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 External Components
      2. 7.3.2 Device Interface Variants
        1. 7.3.2.1 Serial Peripheral Interface (SPI)
        2. 7.3.2.2 Hardware (H/W)
      3. 7.3.3 Input PWM Control Modes
        1. 7.3.3.1 Half-Bridge Control Scheme With Input PWM Mapping
          1. 7.3.3.1.1 DRV8718-Q1 Half-Bridge Control
          2. 7.3.3.1.2 DRV8714-Q1 Half-Bridge Control
        2. 7.3.3.2 H-Bridge Control
          1. 7.3.3.2.1 DRV8714-Q1 H-Bridge Control
        3. 7.3.3.3 Split HS and LS Solenoid Control
          1. 7.3.3.3.1 DRV8714-Q1 Split HS and LS Solenoid Control
      4. 7.3.4 Smart Gate Driver
        1. 7.3.4.1 Functional Block Diagram
        2. 7.3.4.2 Slew Rate Control (IDRIVE)
        3. 7.3.4.3 Gate Drive State Machine (TDRIVE)
        4. 7.3.4.4 Propagation Delay Reduction (PDR)
          1. 7.3.4.4.1 PDR Pre-Charge/Pre-Discharge Control Loop Operation Details
            1. 7.3.4.4.1.1 PDR Pre-Charge/Pre-Discharge Setup
          2. 7.3.4.4.2 PDR Post-Charge/Post-Discharge Control Loop Operation Details
            1. 7.3.4.4.2.1 PDR Post-Charge/Post-Discharge Setup
          3. 7.3.4.4.3 Detecting Drive and Freewheel MOSFET
        5. 7.3.4.5 Automatic Duty Cycle Compensation (DCC)
        6. 7.3.4.6 Closed Loop Slew Time Control (STC)
          1. 7.3.4.6.1 STC Control Loop Setup
      5. 7.3.5 Tripler (Dual-Stage) Charge Pump
      6. 7.3.6 Wide Common-Mode Current Shunt Amplifiers
      7. 7.3.7 Pin Diagrams
        1. 7.3.7.1 Logic Level Input Pin (INx/ENx, INx/PHx, nSLEEP, nSCS, SCLK, SDI)
        2. 7.3.7.2 Logic Level Push Pull Output (SDO)
        3. 7.3.7.3 Logic Level Multi-Function Pin (DRVOFF/nFLT)
        4. 7.3.7.4 Quad-Level Input (GAIN, MODE)
        5. 7.3.7.5 Six-Level Input (IDRIVE, VDS)
      8. 7.3.8 Protection and Diagnostics
        1. 7.3.8.1  Gate Driver Disable (DRVOFF/nFLT and EN_DRV)
        2. 7.3.8.2  Low IQ Powered Off Braking (POB, BRAKE)
        3. 7.3.8.3  Fault Reset (CLR_FLT)
        4. 7.3.8.4  DVDD Logic Supply Power on Reset (DVDD_POR)
        5. 7.3.8.5  PVDD Supply Undervoltage Monitor (PVDD_UV)
        6. 7.3.8.6  PVDD Supply Overvoltage Monitor (PVDD_OV)
        7. 7.3.8.7  VCP Charge Pump Undervoltage Lockout (VCP_UV)
        8. 7.3.8.8  MOSFET VDS Overcurrent Protection (VDS_OCP)
        9. 7.3.8.9  Gate Driver Fault (VGS_GDF)
        10. 7.3.8.10 Thermal Warning (OTW)
        11. 7.3.8.11 Thermal Shutdown (OTSD)
        12. 7.3.8.12 Offline Short Circuit and Open Load Detection (OOL and OSC)
        13. 7.3.8.13 Watchdog Timer
        14. 7.3.8.14 Fault Detection and Response Summary Table
    4. 7.4 Device Functional Modes
      1. 7.4.1 Inactive or Sleep State
      2. 7.4.2 Standby State
      3. 7.4.3 Operating State
    5. 7.5 Programming
      1. 7.5.1 SPI Interface
      2. 7.5.2 SPI Format
      3. 7.5.3 SPI Interface for Multiple Slaves
        1. 7.5.3.1 SPI Interface for Multiple Slaves in Daisy Chain
  9. 8 Register Maps
    1. 8.1 DRV8718-Q1 Register Map
    2. 8.2 DRV8714-Q1 Register Map
    3. 8.3 DRV8718-Q1 Register Descriptions
      1. 8.3.1 DRV8718-Q1_STATUS Registers
      2. 8.3.2 DRV8718-Q1_CONTROL Registers
      3. 8.3.3 DRV8718-Q1_CONTROL_ADV Registers
      4. 8.3.4 DRV8718-Q1_STATUS_ADV Registers
    4. 8.4 DRV8714-Q1 Register Descriptions
      1. 8.4.1 DRV8714-Q1_STATUS Registers
      2. 8.4.2 DRV8714-Q1_CONTROL Registers
      3. 8.4.3 DRV8714-Q1_CONTROL_ADV Registers
      4. 8.4.4 DRV8714-Q1_STATUS_ADV Registers
  10. 9  Application Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Gate Driver Configuration
          1. 9.2.2.1.1 VCP Load Calculation Example
          2. 9.2.2.1.2 IDRIVE Calculation Example
          3. 9.2.2.1.3 tDRIVE Calculation Example
          4. 9.2.2.1.4 Maximum PWM Switching Frequency
        2. 9.2.2.2 Current Shunt Amplifier Configuration
        3. 9.2.2.3 Power Dissipation
      3. 9.2.3 Application Curves
    3. 9.3 Initialization
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Bulk Capacitance Sizing
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device Documentation and Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documents
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum

8.4.3 DRV8714-Q1_CONTROL_ADV Registers

Table 8-109 lists the DRV8714-Q1_CONTROL_ADV registers. All register offset addresses not listed in Table 8-109 should be considered as reserved locations and the register contents should not be modified.

Table 8-109 DRV8714-Q1_CONTROL_ADV Registers
Address Acronym Register Name Section
2Ah AGD_CTRL1 Adaptive gate drive general control functions Go
2Bh PDR_CTRL1 Half-bridge 1 and 2 PDR delay and max current settings Go
2Ch PDR_CTRL2 Half-bridge 3 and 4 PDR delay and max current settings Go
2Dh PDR_CTRL3 Half-bridge 5 and 6 PDR delay and max current settings Go
2Eh PDR_CTRL4 Half-bridge 7 and 8 PDR delay and max current settings Go
2Fh PDR_CTRL5 Half-bridge 1 PDR charge and discharge initial settings. Go
30h PDR_CTRL6 Half-bridge PDR charge and discharge initial settings. Go
31h PDR_CTRL7 Half-bridge 3 PDR charge and discharge initial settings. Go
32h PDR_CTRL8 Half-bridge 4 PDR charge and discharge initial settings. Go
33h PDR_CTRL9 Half-bridge 1 and 2 PDR loop controller gain Go
34h PDR_CTRL10 Half-bridge 3 and 4 PDR loop controller gain Go
35h STC_CTRL1 Half-bridge 1 STC rise/fall time and controller gain Go
36h STC_CTRL2 Half-bridge 2 STC rise/fall time and controller gain Go
37h STC_CTRL3 Half-bridge 3 STC rise/fall time and controller gain Go
38h STC_CTRL4 Half-bridge 4 STC rise/fall time and controller gain Go
39h DCC_CTRL1 Half-bridge 1-4 DCC enable and manual control Go
3Ah PST_CTRL1 Half-bridge 1-4 freewheel and post charge delay control Go
3Bh PST_CTRL2 Half-bridge 1-4 post charge controller gain Go

Complex bit access types are encoded to fit into small table cells. Table 8-110 shows the codes that are used for access types in this section.

Table 8-110 DRV8714-Q1_CONTROL_ADV Access Type Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
Reset or Default Value
- n Value after reset or the default value

8.4.3.1 AGD_CTRL1 Register (Address = 2Ah) [Reset = 40h]

AGD_CTRL1 is shown in Figure 8-93 and described in Table 8-111.

Return to the Summary Table.

Control register for adaptive gate drive voltage thresholds, pull down setting, and active half-bridge configuration.

Figure 8-93 AGD_CTRL1 Register
7 6 5 4 3 2 1 0
AGD_THR AGD_ISTRONG RESERVED
R/W-01b R/W-00b R-0000b
Table 8-111 AGD_CTRL1 Register Field Descriptions
Bit Field Type Reset Description
7-6 AGD_THR R/W 01b Adaptive gate driver VSH threshold configuration.
00b = 1V, VDRAIN - 0.5V
01b = 1V, VDRAIN - 1V
10b = 2V, VDRAIN - 1.5V
11b = 2V, VDRAIN - 2V
5-4 AGD_ISTRONG R/W 00b Adaptive gate driver ISTRONG configuration.
00b = ISTRONG pulldown decoded from initial IDRVP_x register setting.
01b = 62 mA
10b = 124 mA
11b = RSVD
3-0 RESERVED R 0000b Reserved

8.4.3.2 PDR_CTRL1 Register (Address = 2Bh) [Reset = Ah]

PDR_CTRL1 is shown in Figure 8-94 and described in Table 8-112.

Return to the Summary Table.

Control register for tON_OFF propagation delay and pre-charge/discharge max current for half-bridge 1.

Figure 8-94 PDR_CTRL1 Register
7 6 5 4 3 2 1 0
PRE_MAX_1 T_DON_DOFF_1
R/W-00b R/W-001010b
Table 8-112 PDR_CTRL1 Register Field Descriptions
Bit Field Type Reset Description
7-6 PRE_MAX_1 R/W 00b Maximum gate drive current limit for pre-charge and pre-discharge for half-bridge 1.
00b = 64 mA
01b = 32 mA
10b = 16 mA
11b = 8 mA
5-0 T_DON_DOFF_1 R/W 001010b On and off time delay for half-bridge 1. 140 ns x T_DON_DOFF_1 [3:0] Default time: 001010b (1.4 us)

8.4.3.3 PDR_CTRL2 Register (Address = 2Ch) [Reset = Ah]

PDR_CTRL2 is shown in Figure 8-95 and described in Table 8-113.

Return to the Summary Table.

Control register for tON_OFF propagation delay and pre-charge/discharge max current for half-bridge 2.

Figure 8-95 PDR_CTRL2 Register
7 6 5 4 3 2 1 0
PRE_MAX_2 T_DON_DOFF_2
R/W-00b R/W-001010b
Table 8-113 PDR_CTRL2 Register Field Descriptions
Bit Field Type Reset Description
7-6 PRE_MAX_2 R/W 00b Maximum gate drive current limit for pre-charge and pre-discharge for half-bridge 2.
00b = 64 mA
01b = 32 mA
10b = 16 mA
11b = 8 mA
5-0 T_DON_DOFF_2 R/W 001010b On and off time delay for half-bridge 2. 140 ns x T_DON_DOFF_2 [3:0] Default time: 001010b (1.4 us)

8.4.3.4 PDR_CTRL3 Register (Address = 2Dh) [Reset = Ah]

PDR_CTRL3 is shown in Figure 8-96 and described in Table 8-114.

Return to the Summary Table.

Control register for tON_OFF propagation delay and pre-charge/discharge max current for half-bridge 3.

Figure 8-96 PDR_CTRL3 Register
7 6 5 4 3 2 1 0
PRE_MAX_3 T_DON_DOFF_3
R/W-00b R/W-001010b
Table 8-114 PDR_CTRL3 Register Field Descriptions
Bit Field Type Reset Description
7-6 PRE_MAX_3 R/W 00b Maximum gate drive current limit for pre-charge and pre-discharge for half-bridge 3.
00b = 64 mA
01b = 32 mA
10b = 16 mA
11b = 8 mA
5-0 T_DON_DOFF_3 R/W 001010b On and off time delay for half-bridge 3. 140 ns x T_DON_DOFF_3 [3:0] Default time: 001010b (1.4 us)

8.4.3.5 PDR_CTRL4 Register (Address = 2Eh) [Reset = Ah]

PDR_CTRL4 is shown in Figure 8-97 and described in Table 8-115.

Return to the Summary Table.

Control register for tON_OFF propagation delay and pre-charge/discharge max current for half-bridge 4.

Figure 8-97 PDR_CTRL4 Register
7 6 5 4 3 2 1 0
PRE_MAX_4 T_DON_DOFF_4
R/W-00b R/W-001010b
Table 8-115 PDR_CTRL4 Register Field Descriptions
Bit Field Type Reset Description
7-6 PRE_MAX_4 R/W 00b Maximum gate drive current limit for pre-charge and pre-discharge for half-bridge 4.
00b = 64 mA
01b = 32 mA
10b = 16 mA
11b = 8 mA
5-0 T_DON_DOFF_4 R/W 001010b On and off time delay for half-bridge 4. 140 ns x T_DON_DOFF_4 [3:0] Default time: 001010b (1.4 us)

8.4.3.6 PDR_CTRL5 Register (Address = 2Fh) [Reset = F6h]

PDR_CTRL5 is shown in Figure 8-98 and described in Table 8-116.

Return to the Summary Table.

Control register for charge and pre-charge initial settings for half-bridge 1.

Figure 8-98 PDR_CTRL5 Register
7 6 5 4 3 2 1 0
T_PRE_CHR_1 T_PRE_DCHR_1 PRE_CHR_INIT_1 PRE_DCHR_INIT_1
R/W-11b R/W-11b R/W-01b R/W-10b
Table 8-116 PDR_CTRL5 Register Field Descriptions
Bit Field Type Reset Description
7-6 T_PRE_CHR_1 R/W 11b PDR control loop pre-charge time for half-bridge 1. Set as ratio of T_DON_DOFF_1 [5:0]
00b = 1/8
01b = 1/4
10b = 3/8
11b = 1/2
5-4 T_PRE_DCHR_1 R/W 11b PDR control loop pre-discharge time for half-bridge 1. Set as ratio of T_DON_DOFF_1 [5:0]
00b = 1/8
01b = 1/4
10b = 3/8
11b = 1/2
3-2 PRE_CHR_INIT_1 R/W 01b PDR control loop initial pre-charge current setting for half-bridge 1.
00b = 4 mA
01b = 8 mA
10b = 16 mA
11b = 32 mA
1-0 PRE_DCHR_INIT_1 R/W 10b PDR control loop initial pre-discharge current setting for half-bridge 1.
00b = 4 mA
01b = 8 mA
10b = 16 mA
11b = 32 mA

8.4.3.7 PDR_CTRL6 Register (Address = 30h) [Reset = F6h]

PDR_CTRL6 is shown in Figure 8-99 and described in Table 8-117.

Return to the Summary Table.

Control register for charge and pre-charge initial settings for half-bridge 2.

Figure 8-99 PDR_CTRL6 Register
7 6 5 4 3 2 1 0
T_PRE_CHR_2 T_PRE_DCHR_2 PRE_CHR_INIT_2 PRE_DCHR_INIT_2
R/W-11b R/W-11b R/W-01b R/W-10b
Table 8-117 PDR_CTRL6 Register Field Descriptions
Bit Field Type Reset Description
7-6 T_PRE_CHR_2 R/W 11b PDR control loop pre-charge time for half-bridge 2. Set as ratio of T_DON_DOFF_2 [5:0]
00b = 1/8
01b = 1/4
10b = 3/8
11b = 1/2
5-4 T_PRE_DCHR_2 R/W 11b PDR control loop pre-discharge time for half-bridge 2. Set as ratio of T_DON_DOFF_2 [5:0]
00b = 1/8
01b = 1/4
10b = 3/8
11b = 1/2
3-2 PRE_CHR_INIT_2 R/W 01b PDR control loop initial pre-charge current setting for half-bridge 2.
00b = 4 mA
01b = 8 mA
10b = 16 mA
11b = 32 mA
1-0 PRE_DCHR_INIT_2 R/W 10b PDR control loop initial pre-discharge current setting for half-bridge 2.
00b = 4 mA
01b = 8 mA
10b = 16 mA
11b = 32 mA

8.4.3.8 PDR_CTRL7 Register (Address = 31h) [Reset = F6h]

PDR_CTRL7 is shown in Figure 8-100 and described in Table 8-118.

Return to the Summary Table.

Control register for charge and pre-charge initial settings for half-bridge 3.

Figure 8-100 PDR_CTRL7 Register
7 6 5 4 3 2 1 0
T_PRE_CHR_3 T_PRE_DCHR_3 PRE_CHR_INIT_3 PRE_DCHR_INIT_3
R/W-11b R/W-11b R/W-01b R/W-10b
Table 8-118 PDR_CTRL7 Register Field Descriptions
Bit Field Type Reset Description
7-6 T_PRE_CHR_3 R/W 11b PDR control loop pre-charge time for half-bridge 3. Set as ratio of T_DON_DOFF_3 [5:0]
00b = 1/8
01b = 1/4
10b = 3/8
11b = 1/2
5-4 T_PRE_DCHR_3 R/W 11b PDR control loop pre-discharge time for half-bridge 3. Set as ratio of T_DON_DOFF_3 [5:0]
00b = 1/8
01b = 1/4
10b = 3/8
11b = 1/2
3-2 PRE_CHR_INIT_3 R/W 01b PDR control loop initial pre-charge current setting for half-bridge 3.
00b = 4 mA
01b = 8 mA
10b = 16 mA
11b = 32 mA
1-0 PRE_DCHR_INIT_3 R/W 10b PDR control loop initial pre-discharge current setting for half-bridge 3.
00b = 4 mA
01b = 8 mA
10b = 16 mA
11b = 32 mA

8.4.3.9 PDR_CTRL8 Register (Address = 32h) [Reset = F6h]

PDR_CTRL8 is shown in Figure 8-101 and described in Table 8-119.

Return to the Summary Table.

Control register for charge and pre-charge initial settings for half-bridge 4.

Figure 8-101 PDR_CTRL8 Register
7 6 5 4 3 2 1 0
T_PRE_CHR_4 T_PRE_DCHR_4 PRE_CHR_INIT_4 PRE_DCHR_INIT_4
R/W-11b R/W-11b R/W-01b R/W-10b
Table 8-119 PDR_CTRL8 Register Field Descriptions
Bit Field Type Reset Description
7-6 T_PRE_CHR_4 R/W 11b PDR control loop pre-charge time for half-bridge 4. Set as ratio of T_DON_DOFF_4 [5:0]
00b = 1/8
01b = 1/4
10b = 3/8
11b = 1/2
5-4 T_PRE_DCHR_4 R/W 11b PDR control loop pre-discharge time for half-bridge 4. Set as ratio of T_DON_DOFF_4 [5:0]
00b = 1/8
01b = 1/4
10b = 3/8
11b = 1/2
3-2 PRE_CHR_INIT_4 R/W 01b PDR control loop initial pre-charge current setting for half-bridge 4.
00b = 4 mA
01b = 8 mA
10b = 16 mA
11b = 32 mA
1-0 PRE_DCHR_INIT_4 R/W 10b PDR control loop initial pre-discharge current setting for half-bridge 4.
00b = 4 mA
01b = 8 mA
10b = 16 mA
11b = 32 mA

8.4.3.10 PDR_CTRL9 Register (Address = 33h) [Reset = 11h]

PDR_CTRL9 is shown in Figure 8-102 and described in Table 8-120.

Return to the Summary Table.

Control register to configure PDR Kp loop controller gain setting for half-bridges 1 and 2.

Figure 8-102 PDR_CTRL9 Register
7 6 5 4 3 2 1 0
EN_PDR_1 PDR_ERR_1 KP_PDR_1 EN_PDR_2 PDR_ERR_2 KP_PDR_2
R/W-0b R/W-0b R/W-01b R/W-0b R/W-0b R/W-01b
Table 8-120 PDR_CTRL9 Register Field Descriptions
Bit Field Type Reset Description
7 EN_PDR_1 R/W 0b Enable PDR loop control for half-bridge 1.
6 PDR_ERR_1 R/W 0b PDR loop error limit for half-bridge 1.
0b = 1-bit error
1b = Actual error
5-4 KP_PDR_1 R/W 01b PDR proportional controller gain setting for half-bridge 1.
00b = 1
01b = 2
10b = 3
11b = 4
3 EN_PDR_2 R/W 0b Enable PDR loop control for half-bridge 2.
2 PDR_ERR_2 R/W 0b PDR loop error limit for half-bridge 2.
0b = 1-bit error
1b = Actual error
1-0 KP_PDR_2 R/W 01b PDR proportional controller gain setting for half-bridge 2.
00b = 1
01b = 2
10b = 3
11b = 4

8.4.3.11 PDR_CTRL10 Register (Address = 34h) [Reset = 11h]

PDR_CTRL10 is shown in Figure 8-103 and described in Table 8-121.

Return to the Summary Table.

Control register to configure PDR Kp loop controller gain setting for half-bridges 3 and 4.

Figure 8-103 PDR_CTRL10 Register
7 6 5 4 3 2 1 0
EN_PDR_3 PDR_ERR_3 KP_PDR_3 EN_PDR_4 PDR_ERR_4 KP_PDR_4
R/W-0b R/W-0b R/W-01b R/W-0b R/W-0b R/W-01b
Table 8-121 PDR_CTRL10 Register Field Descriptions
Bit Field Type Reset Description
7 EN_PDR_3 R/W 0b Enable PDR loop control for half-bridge 3.
6 PDR_ERR_3 R/W 0b PDR loop error limit for half-bridge 3.
0b = 1-bit error
1b = Actual error
5-4 KP_PDR_3 R/W 01b PDR proportional controller gain setting for half-bridge 3.
00b = 1
01b = 2
10b = 3
11b = 4
3 EN_PDR_4 R/W 0b Enable PDR loop control for half-bridge 4.
2 PDR_ERR_4 R/W 0b PDR loop error limit for half-bridge 4.
0b = 1-bit error
1b = Actual error
1-0 KP_PDR_4 R/W 01b PDR proportional controller gain setting for half-bridge 4.
00b = 1
01b = 2
10b = 3
11b = 4

8.4.3.12 STC_CTRL1 Register (Address = 35h) [Reset = 23h]

STC_CTRL1 is shown in Figure 8-104 and described in Table 8-122.

Return to the Summary Table.

Control register to configure STC rise/fall time and Kp loop controller gain setting for half-bridge 1.

Figure 8-104 STC_CTRL1 Register
7 6 5 4 3 2 1 0
T_RISE_FALL_1 EN_STC_1 STC_ERR_1 KP_STC_1
R/W-0010b R/W-0b R/W-0b R/W-11b
Table 8-122 STC_CTRL1 Register Field Descriptions
Bit Field Type Reset Description
7-4 T_RISE_FALL_1 R/W 0010b Set switch-node VSH rise and fall time for half-bridge 1.
0000b = 0.35 us
0001b = 0.56 us
0010b = 0.77 us
0011b = 0.98 us
0100b = 1.33 us
0101b = 1.68 us
0110b = 2.03 us
0111b = 2.45 us
1000b = 2.94 us
1001b = 3.99 us
1010b = 4.97 us
1011b = 5.95 us
1100b = 7.98 us
1101b = 9.94 us
1110b = 11.97 us
1111b = 15.96 us
3 EN_STC_1 R/W 0b Enable STC loop control for half-bridge 1.
2 STC_ERR_1 R/W 0b STC loop error limit for half-bridge 1.
0b = 1-bit error
1b = Actual error
1-0 KP_STC_1 R/W 11b STC proportional controller gain setting for half-bridge 1.
00b = 1
01b = 2
10b = 3
11b = 4

8.4.3.13 STC_CTRL2 Register (Address = 36h) [Reset = 23h]

STC_CTRL2 is shown in Figure 8-105 and described in Table 8-123.

Return to the Summary Table.

Control register to configure STC rise/fall time and Kp loop controller gain setting for half-bridge 2.

Figure 8-105 STC_CTRL2 Register
7 6 5 4 3 2 1 0
T_RISE_FALL_2 EN_STC_2 STC_ERR_2 KP_STC_2
R/W-0010b R/W-0b R/W-0b R/W-11b
Table 8-123 STC_CTRL2 Register Field Descriptions
Bit Field Type Reset Description
7-4 T_RISE_FALL_2 R/W 0010b Set switch-node VSH rise and fall time for half-bridge 2.
0000b = 0.35 us
0001b = 0.56 us
0010b = 0.77 us
0011b = 0.98 us
0100b = 1.33 us
0101b = 1.68 us
0110b = 2.03 us
0111b = 2.45 us
1000b = 2.94 us
1001b = 3.99 us
1010b = 4.97 us
1011b = 5.95 us
1100b = 7.98 us
1101b = 9.94 us
1110b = 11.97 us
1111b = 15.96 us
3 EN_STC_2 R/W 0b Enable STC loop control for half-bridge 2.
2 STC_ERR_2 R/W 0b STC loop error limit for half-bridge 2.
0b = 1-bit error
1b = Actual error
1-0 KP_STC_2 R/W 11b STC proportional controller gain setting for half-bridge 2.
00b = 1
01b = 2
10b = 3
11b = 4

8.4.3.14 STC_CTRL3 Register (Address = 37h) [Reset = 23h]

STC_CTRL3 is shown in Figure 8-106 and described in Table 8-124.

Return to the Summary Table.

Control register to configure STC rise/fall time and Kp loop controller gain setting for half-bridge 3.

Figure 8-106 STC_CTRL3 Register
7 6 5 4 3 2 1 0
T_RISE_FALL_3 EN_STC_3 STC_ERR_3 KP_STC_3
R/W-0010b R/W-0b R/W-0b R/W-11b
Table 8-124 STC_CTRL3 Register Field Descriptions
Bit Field Type Reset Description
7-4 T_RISE_FALL_3 R/W 0010b Set switch-node VSH rise and fall time for half-bridge 3.
0000b = 0.35 us
0001b = 0.56 us
0010b = 0.77 us
0011b = 0.98 us
0100b = 1.33 us
0101b = 1.68 us
0110b = 2.03 us
0111b = 2.45 us
1000b = 2.94 us
1001b = 3.99 us
1010b = 4.97 us
1011b = 5.95 us
1100b = 7.98 us
1101b = 9.94 us
1110b = 11.97 us
1111b = 15.96 us
3 EN_STC_3 R/W 0b Enable STC loop control for half-bridge 3.
2 STC_ERR_3 R/W 0b STC loop error limit for half-bridge 3.
0b = 1-bit error
1b = Actual error
1-0 KP_STC_3 R/W 11b STC proportional controller gain setting for half-bridge 3.
00b = 1
01b = 2
10b = 3
11b = 4

8.4.3.15 STC_CTRL4 Register (Address = 38h) [Reset = 23h]

STC_CTRL4 is shown in Figure 8-107 and described in Table 8-125.

Return to the Summary Table.

Control register to configure STC rise/fall time and Kp loop controller gain setting for half-bridge 4.

Figure 8-107 STC_CTRL4 Register
7 6 5 4 3 2 1 0
T_RISE_FALL_4 EN_STC_4 STC_ERR_4 KP_STC_4
R/W-0010b R/W-0b R/W-0b R/W-11b
Table 8-125 STC_CTRL4 Register Field Descriptions
Bit Field Type Reset Description
7-4 T_RISE_FALL_4 R/W 0010b Set switch-node VSH rise and fall time for half-bridge 4.
0000b = 0.35 us
0001b = 0.56 us
0010b = 0.77 us
0011b = 0.98 us
0100b = 1.33 us
0101b = 1.68 us
0110b = 2.03 us
0111b = 2.45 us
1000b = 2.94 us
1001b = 3.99 us
1010b = 4.97 us
1011b = 5.95 us
1100b = 7.98 us
1101b = 9.94 us
1110b = 11.97 us
1111b = 15.96 us
3 EN_STC_4 R/W 0b Enable STC loop control for half-bridge 4.
2 STC_ERR_4 R/W 0b STC loop error limit for half-bridge 4.
0b = 1-bit error
1b = Actual error
1-0 KP_STC_4 R/W 11b STC proportional controller gain setting for half-bridge 4.
00b = 1
01b = 2
10b = 3
11b = 4

8.4.3.16 DCC_CTRL1 Register (Address = 39h) [Reset = 0h]

DCC_CTRL1 is shown in Figure 8-108 and described in Table 8-126.

Return to the Summary Table.

Control register to enable DCC loop and manual configuration for half-bridges 1-4.

Figure 8-108 DCC_CTRL1 Register
7 6 5 4 3 2 1 0
EN_DCC_1 EN_DCC_2 EN_DCC_3 EN_DCC_4 IDIR_MAN_1 IDIR_MAN_2 IDIR_MAN_3 IDIR_MAN_4
R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b
Table 8-126 DCC_CTRL1 Register Field Descriptions
Bit Field Type Reset Description
7 EN_DCC_1 R/W 0b Enable duty cycle compensation for half-bridge 1.
6 EN_DCC_2 R/W 0b Enable duty cycle compensation for half-bridge 2.
5 EN_DCC_3 R/W 0b Enable duty cycle compensation for half-bridge 3.
4 EN_DCC_4 R/W 0b Enable duty cycle compensation for half-bridge 4.
3 IDIR_MAN_1 R/W 0b Current polarity detection mode for half-bridge 1.
0b = Automatic
1b = Manual (Set by HBx_HL)
2 IDIR_MAN_2 R/W 0b Current polarity detection mode for half-bridge 2.
0b = Automatic
1b = Manual (Set by HBx_HL)
1 IDIR_MAN_3 R/W 0b Current polarity detection mode for half-bridge 3.
0b = Automatic
1b = Manual (Set by HBx_HL)
0 IDIR_MAN_4 R/W 0b Current polarity detection mode for half-bridge 4.
0b = Automatic
1b = Manual (Set by HBx_HL)

8.4.3.17 PST_CTRL1 Register (Address = 3Ah) [Reset = Fh]

PST_CTRL1 is shown in Figure 8-109 and described in Table 8-127.

Return to the Summary Table.

Control register to configure max freewheeling current and post charge delay for half-bridges 1-4.

Figure 8-109 PST_CTRL1 Register
7 6 5 4 3 2 1 0
FW_MAX_1 FW_MAX_2 FW_MAX_3 FW_MAX_4 EN_PST_DLY_1 EN_PST_DLY_2 EN_PST_DLY_3 EN_PST_DLY_4
R/W-0b R/W-0b R/W-0b R/W-0b R/W-1b R/W-1b R/W-1b R/W-1b
Table 8-127 PST_CTRL1 Register Field Descriptions
Bit Field Type Reset Description
7 FW_MAX_1 R/W 0b Gate drive current used for freewheeling MOSFET for half-bridge 1.
0b = PRE_CHR_MAX_1 [1:0] 1b = 64 mA
6 FW_MAX_2 R/W 0b Gate drive current used for freewheeling MOSFET for half-bridge 2.
0b = PRE_CHR_MAX_2 [1:0] 1b = 64 mA
5 FW_MAX_3 R/W 0b Gate drive current used for freewheeling MOSFET for half-bridge 3.
0b = PRE_CHR_MAX_3 [1:0] 1b = 64 mA
4 FW_MAX_4 R/W 0b Gate drive current used for freewheeling MOSFET for half-bridge 4.
0b = PRE_CHR_MAX_4 [1:0] 1b = 64 mA
3 EN_PST_DLY_1 R/W 1b Enable post-charge time delay. Time delay is equal to T_DON_DOFF_1 - T_PRE_CHR_1.
2 EN_PST_DLY_2 R/W 1b Enable post-charge time delay. Time delay is equal to T_DON_DOFF_2 - T_PRE_CHR_2.
1 EN_PST_DLY_3 R/W 1b Enable post-charge time delay. Time delay is equal to T_DON_DOFF_3 - T_PRE_CHR_3.
0 EN_PST_DLY_4 R/W 1b Enable post-charge time delay. Time delay is equal to T_DON_DOFF_4 - T_PRE_CHR_4.

8.4.3.18 PST_CTRL2 Register (Address = 3Bh) [Reset = 55h]

PST_CTRL2 is shown in Figure 8-110 and described in Table 8-128.

Return to the Summary Table.

Control register to configure post charge Kp loop controller gain setting for half-bridges 1-4.

Figure 8-110 PST_CTRL2 Register
7 6 5 4 3 2 1 0
KP_PST_1 KP_PST_2 KP_PST_3 KP_PST_4
R/W-01b R/W-01b R/W-01b R/W-01b
Table 8-128 PST_CTRL2 Register Field Descriptions
Bit Field Type Reset Description
7-6 KP_PST_1 R/W 01b Post charge proportional control gain setting for half-bridge 1.
00b = Disabled
01b = 2
10b = 4
11b = 15
5-4 KP_PST_2 R/W 01b Post charge proportional control gain setting for half-bridge 2.
00b = Disabled
01b = 2
10b = 4
11b = 15
3-2 KP_PST_3 R/W 01b Post charge proportional control gain setting for half-bridge 3.
00b = Disabled
01b = 2
10b = 4
11b = 15
1-0 KP_PST_4 R/W 01b Post charge proportional control gain setting for half-bridge 4.
00b = Disabled
01b = 2
10b = 4
11b = 15