JAJSL15N July   1997  – April 2021 SN55LVDS31 , SN65LVDS31 , SN65LVDS3487 , SN65LVDS9638

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. 概要 (続き)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings #GUID-35E89C88-1E48-404C-8AB6-22CCA817C2ED/SLLS2613609
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: SN55LVDS31
    6. 7.6 Electrical Characteristics: SN65LVDSxxxx
    7. 7.7 Switching Characteristics: SN55LVDS31
    8. 7.8 Switching Characteristics: SN65LVDSxxxx
    9. 7.9 Typical Characteristics
      1. 7.9.1 17
  8. Parameter Measurement Information
    1. 8.1 19
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Driver Disabled Output
      2. 9.3.2 NC Pins
      3. 9.3.3 Unused Enable Pins
      4. 9.3.4 Driver Equivalent Schematics
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Point-to-Point Communications
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Driver Supply Voltage
          2. 10.2.1.2.2 Driver Bypass Capacitance
          3. 10.2.1.2.3 Driver Output Voltage
          4. 10.2.1.2.4 Interconnecting Media
          5. 10.2.1.2.5 PCB Transmission Lines
          6. 10.2.1.2.6 Termination Resistor
          7. 10.2.1.2.7 Driver NC Pins
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Multidrop Communications
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
          1. 10.2.2.2.1 Interconnecting Media
        3. 10.2.2.3 Application Curve
  11. 11Power Supply Recommendations
    1. 11.1 49
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Microstrip vs. Stripline Topologies
      2. 12.1.2 Dielectric Type and Board Construction
      3. 12.1.3 Recommended Stack Layout
      4. 12.1.4 Separation Between Traces
      5. 12.1.5 Crosstalk and Ground Bounce Minimization
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Other LVDS Products
    2. 13.2 Documentation Support
      1. 13.2.1 Related Information
      2. 13.2.2 ドキュメントの更新通知を受け取る方法
      3. 13.2.3 Related Links
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 用語集
  14. 14Mechanical, Packaging, and Orderable Information
Interconnecting Media

The interconnect in a multidrop system differs considerably from a point-to-point system. While point-to-point interconnects are straightforward and well understood, the bus type architecture encountered with multidrop systems requires more careful attention. We will use Figure 10-6 above to explore these details.

The most basic multidrop system would include a single driver, located at a bus origin, with multiple receiver nodes branching off the main line, and a final receiver at the end of the transmission line, co-located with a bus termination resistor. While this would be the most basic multidrop system, it has several considerations not yet explored.

The location of the transmitter at one bus end allows the design concerns to be simplified, but this comes at the cost of flexibility. With a transmitter located at the origin, a single bus termination at the far-end is required. The far-end termination absorbs the incident traveling wave. The flexibility lost with this arrangement is thus: if the single transmitter needed to be relocated on the bus, at any location other than the origin, we would be faced with a bus with one open-circuited end, and one properly terminated end. Locating the transmitter say in the middle of the bus may be desired to reduce (by ½) the maximum flight time from the transmitter to receiver.

Another new feature in Figure 10-6 is clear in that every node branching off the main line results in stubs. The stubs should be minimized in any case, but have the unintended effect of locally changing the loaded impedance of the bus.

To a good approximation, the characteristic transmission line impedance seen into any cut point in the unloaded multipoint or multidrop bus is defined by √ L/C, where L is the inductance per unit length and C is the capacitance per unit length. As capacitance is added to the bus in the form of devices and interconnections, the bus characteristic impedance is lowered. This may result in signal reflections from the impedance mismatch between the unloaded and loaded segments of the bus.

If the number of loads is constant and can be distributed evenly along the line, reflections can be reduced by changing the bus termination resistors to match the loaded characteristic impedance. Normally, the number of loads are not constant or distributed evenly and the reflections resulting from any mismatching should be accounted for in the noise budget.