JAJSL37 December   2021 AMC1351

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Timing Diagram
    12. 6.12 Insulation Characteristics Curves
    13. 6.13 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
      2. 7.3.2 Isolation Channel Signal Transmission
      3. 7.3.3 Analog Output
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Filter Design
        2. 8.2.2.2 Differential to Single-Ended Output Conversion
      3. 8.2.3 Application Curve
    3. 8.3 What To Do and What Not To Do
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

6.9 Electrical Characteristics

minimum and maximum specifications apply from TA = –40°C to +125°C, VDD1 = 3.0 V to 5.5 V, VDD2 = 3.0 V to 5.5 V, IN = –0.25 V to +5 V (unless otherwise noted); typical specifications are at TA = 25°C, VDD1 = 5 V, and VDD2 = 3.3 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
VOS Offset voltage(2) TA = 25°C, IN = GND1,
4.5 V ≤ VDD1 ≤ 5.5 V(1)		 –1.5 ±0.3 1.5 mV
TA = 25°C, IN = GND1,
3.0 V ≤ VDD1 ≤ 5.5 V(3)		 –2.5 –0.8 2.5
ΔVOS Offset voltage long-term stability 10 years at TA = 55℃ 0(7) mV
TCVOS Offset voltage thermal drift(6) IN = GND1 –15 ±3 15 µV/°C
ΔTCVOS Offset voltage thermal drift
long-term stability		 10 years at TA = 55℃,
IN = GND1		 0(7) mV/°C
RIN Input resistance 1 1.25 1.5 MΩ
ΔRIN Input resistance long-term stability 10 years at TA = 55℃ 0(7) ppm
TCRIN Input resistance thermal drift –40℃ ≤ TA ≤ 85℃ 5 ppm/°C
CIN Input capacitance fIN = 275 kHz 4 pF
ANALOG OUTPUT
Nominal gain 0.40 V/V
EG Gain error(1) TA = 25℃ –0.2% ±0.05% 0.2%
ΔEG Gain error long-term stability 10 years at TA = 55℃ 0(7)
TCEG Gain error thermal drift(1)(7) –35 ±10 35 ppm/°C
ΔTCEG Gain error thermal drift
long-term stability		 10 years at TA = 55℃ 0(7) ppm/°C
Nonlineartity(1) –0.02% ±0.003% 0.02%
Nonlinearity thermal drift 0.2 ppm/°C
THD Total harmonic distortion(4) VIN = 5 VPP, fIN = 10 kHz,
BW = 100 kHz		 –82 dB
SNR Signal-to-noise ratio VIN = 5 VPP, fIN = 1 kHz,
BW = 10 kHz		 75 79 dB
VIN = 5 VPP, fIN = 10 kHz,
BW = 100 kHz		 69
Output noise IN = GND1, BW = 100 kHz 250 µVrms
PSRR Power-supply rejection ratio(2) PSRR vs VDD1, DC –67 dB
PSRR vs VDD2, DC –80
PSRR vs VDD1 with 10-kHz,
100-mV ripple		 –65
PSRR vs VDD2 with 10-kHz,
100-mV ripple		 –64
VCMout Output common-mode voltage 1.39 1.44 1.49 V
VCLIPout Clipping differential output voltage VOUT = (VOUTP – VOUTN),
VIN > VClipping		 2.49 V
VFail-safe Fail-safe differential output voltage VDD1 undervoltage or VDD1 missing –2.57 –2.5 V
BW Output bandwidth 275 300 kHz
ROUT Output resistance On OUTP or OUTN < 0.2 Ω
Output short-circuit current On OUTP or OUTN, sourcing or sinking,
IN = GND1, outputs shorted to
either GND or VDD2		 14 mA
CMTI Common-mode transient immunity 100 150 kV/µs
POWER SUPPLY
VDD1UV VDD1 undervoltage detection threshold VDD1 rising 2.5 2.7 2.9 V
VDD1 falling 2.4 2.6 2.8
VDD2UV VDD2 undervoltage detection threshold VDD2 rising 2.2 2.45 2.65 V
VDD2 falling 1.85 2.0 2.2
IDD1 High-side supply current 3.0 V < VDD1 < 3.6 V 6.0 8.1 mA
4.5 V < VDD1 < 5.5 V 7.0 9.3
IDD2 Low-side supply current 3.0 V < VDD2 < 3.6 V 5.3 7.2 mA
4.5 V < VDD2 < 5.5 V 5.9 8.1
(1) The typical value includes one standard deviation (sigma) at nominal operating conditions.
(2) This parameter is input referred.
(3) The typical value is at VDD1 = 3.3 V.
(4) THD is the ratio of the rms sum of the amplitues of first five higher harmonics to the amplitude of the fundamental.
(5) Offset error temperature drift is calculated using the box method, as described by the following equation:
TCVOS = (VOS,MAX - VOS,MIN) / TempRange where VOS,MAX and VOS,MIN refer to the maximum and minimum VOS values measured within the temperature range (–40 to 125℃).
(6) Gain error temperature drift is calculated using the box method, as described by the following equation:
TCEG (ppm) = ((EG,MAX - EG,MIN) / TempRange) x 104 where EG,MAX and EG,MIN refer to the maximum and minimum EG values (in %) measured within the temperature range (–40 to 125℃).
(7) Value is below measurement capability.