JAJSL78D september   2009  – may 2021 BQ24050 , BQ24052

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings #GUID-2D40D94D-8E9B-4250-B39D-57145C9518DB/SLUS9405873
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions #GUID-C5354C38-DF78-4F74-91ED-68706C55D3F9/SLUS9401392
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
      1. 6.8.1 Power Up, Down, OVP, Disable and Enable Waveforms
      2. 6.8.2 Protection Circuits Waveforms
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power Down, or Undervoltage Lockout (UVLO)
      2. 7.3.2  Power Up
      3. 7.3.3  D+, D– Detection
      4. 7.3.4  New Charge Cycle
      5. 7.3.5  Overvoltage Protection (OVP) – Continuously Monitored
      6. 7.3.6  CHG Pin Indication
      7. 7.3.7  CHG LED Pullup Source
      8. 7.3.8  Input DPM Mode (VIN-DPM or IN-DPM)
      9. 7.3.9  OUT
      10. 7.3.10 ISET
      11. 7.3.11 TS
      12. 7.3.12 Termination and Timer Disable Mode (TTDM) -TS Pin High
      13. 7.3.13 Timers
      14. 7.3.14 Termination
      15. 7.3.15 Battery Detect Routine
      16. 7.3.16 Refresh Threshold
      17. 7.3.17 Starting a Charge on a Full Battery
    4. 7.4 Device Functional Modes
      1. 7.4.1 Sleep Mode
    5. 7.5 Programming
      1. 7.5.1 PRE_TERM – Precharge and Termination Programmable Threshold
      2. 7.5.2 ISET2
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 BQ2405x Charger Application Design Example
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Program the Fast Charge Current, ISET
          2. 8.2.1.2.2 Program the Termination Current Threshold, ITERM
          3. 8.2.1.2.3 TS Function
          4. 8.2.1.2.4 CHG
          5. 8.2.1.2.5 Selecting IN and OUT Pin Capacitors
        3. 8.2.1.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
      1. 10.3.1 Leakage Current Effects on Battery Capacity
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 サード・パーティ製品に関する免責事項
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 用語集
  13.   Mechanical, Packaging, and Orderable Information

6.5 Electrical Characteristics

Over junction temperature range 0°C ≤ TJ ≤ 125°C and recommended supply voltage (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT
UVLO Undervoltage lock-out Exit VIN: 0V → 4V Update based on sim/char 3.15 3.3 3.45 V
VHYS_UVLO Hysteresis on VUVLO_RISE falling VIN: 4V→0V,
VUVLO_FALL = VUVLO_RISE –VHYS-UVLO		 175 230 280 mV
VIN-DT Input power good detection threshold is VOUT + VIN-DT (Input power good if VIN > VOUT + VIN-DT);
VOUT = 3.6V, VIN: 3.5V → 4V		 30 80 145 mV
VHYS-INDT Hysteresis on VIN-DT falling VOUT = 3.6V, VIN: 4V → 3.5V 31 mV
VOVP Input overvoltage protection threshold VIN: 5V → 7V (50/52) 6.5 6.65 6.8 V
VHYS-OVP Hysteresis on OVP VIN: 11V → 5V 95 mV
VIN-DPM USB/Adaptor low input voltage protection. Restricts lout at VIN-DPM Feature active in USB mode; Limit Input Source Current to 50mA; VOUT = 3.5V; RISET = 825Ω 4.34 4.4 4.46 V
Feature active in Adaptor mode; Limit Input Source Current to 50mA; VOUT = 3 .5V;
RISET = 825Ω		 4.24 4.3 4.36
IIN-USB-CL USB input I-Limit 100 mA ISET2 = Float; RISET = 825Ω 85 92 100 mA
USB input I-Limit 500 mA ISET2 = High; RISET = 825Ω 430 462 500
ISET SHORT CIRCUIT TEST
RISET_SHORT Highest Resistor value considered a fault (short). Monitored for Iout>90mA Riset: 600Ω → 250Ω, Iout latches off. Cycle power to Reset. USB100 mode. 280 500 Ω
IOUT_CL Maximum OUT current limit Regulation (Clamp) VIN = 5V, VOUT = 3.6V, VISET2 = Low, Riset: 600Ω → 250Ω, IOUT latches off after tDGL-SHORT 1.05 1.4 A
BATTERY SHORT PROTECTION
VOUT(SC) OUT pin short-circuit detection threshold/ precharge threshold VOUT: 3V → 0.5V, no deglitch 0.75 0.8 0.85 V
VOUT(SC-HYS) OUT pin Short hysteresis Recovery ≥ VOUT(SC) + VOUT(SC-HYS);
Rising, no Deglitch		 77 mV
IOUT(SC) Source current to OUT pin during short-circuit detection 10 15 20 mA
QUIESCENT CURRENT
IOUT(PDWN) Battery current into OUT pin VIN = 0V 1 μA
IOUT(DONE) OUT pin current, charging terminated VIN = 6V, VOUT > VOUT(REG) 6
IIN(STDBY) Standby current into IN pin TS = LO, VIN ≤ 6V 125 μA
ICC Active supply current, IN pin TS = open, VIN = 6V, TTDM – no load on OUT pin, VOUT > VOUT(REG), IC enabled 0.8 1 mA
BATTERY CHARGER FAST-CHARGE
VOUT(REG) Battery regulation voltage VIN = 5.5V, IOUT = 25mA, VTS-45°C ≤ VTS ≤ VTS-0°C 4.16 4.20 4.23 V
VO_HT(REG) Battery hot regulation Voltage VIN = 5.5V, IOUT = 25mA, VTS-60°C ≤ VTS ≤ VTS-45°C 4.02 4.06 4.1 V
IOUT(RANGE) Programmed Output “fast charge” current range VOUT(REG) > VOUT > VLOWV, VIN = 5V, ISET2=Lo, RISET = 675 to 10.8kΩ 10 800 mA
VDO(IN-OUT) Drop-Out, VIN – VOUT Adjust VIN down until IOUT = 0.5A, VOUT = 4.15V, RISET = 675 , ISET2 = Lo (Adaptor Mode);
Tj ≤ 100°C		 325 500 mV
IOUT Output “fast charge” formula VOUT(REG) > VOUT > VLOWV, VIN = 5V, ISET2 = Lo KISET/RISET A
KISET Fast charge current factor RISET = KISET /IOUT 50 < IOUT < 1 A 510 540 570 AΩ
RISET = KISET /IOUT 25 < IOUT < 50 mA 480 527 600
RISET = KISET /IOUT 10 < IOUT < 25 mA 350 520 680
PRECHARGE – SET BY PRETERM PIN
VLOWV Precharge to fast-charge transition threshold 2.4 2.5 2.6 V
tDGL1(LOWV) Deglitch time on precharge to fast-charge transition 70 μs
IPRE-TERM Refer to the Termination Section
%PRECHG Precharge Current Level, Default Setting VOUT < VLOWV; RPRE-TERM = High Z (≥13kΩ);
RISET = 1k		 18 20 22 %IOUT-CC
Precharge current formula RPRE-TERM = KPRE-CHG (Ω/%) × %PRE-CHG (%) RPRE-TERM/KPRE-CHG
KPRE-CHG % Precharge Factor VOUT < VLOWV, VIN = 5V, RPRE-TERM = 2k to 10kΩ; RISET = 1080Ω , RPRE-TERM = KPRE-CHG × %IFAST-CHG, where %IFAST-CHG is 20 to 100% 90 100 110 Ω/%
VOUT < VLOWV, VIN = 5V, RPRE-TERM = 1k to 2kΩ; RISET = 1080Ω, RPRE-TERM = KPRE-CHG × %IFAST-CHG, where %IFAST-CHG is 10% to 20% 84 100 117 Ω/%
TERMINATION – SET BY PRE-TERM PIN
%TERM Termination Current Threshold, Default Setting VOUT > VRCH; RPRE-TERM = High Z (≥13kΩ);
RISET = 1k		 9 10 11 %IOUT-CC
Termination Current Threshold Formula RPRE-TERM = KTERM (Ω/%) × %TERM (%) RPRE-TERM/ KTERM
KTERM % Term Factor VOUT > VRCH, VIN = 5V, RPRE-TERM = 2k to 10kΩ ; RISET = 750Ω; KTERM × %IFAST-CHG,
where %IFAST-CHG is 10 to 50%		 182 200 216 Ω/%
VOUT > VRCH, VIN = 5V, RPRE-TERM = 1k to 2kΩ ; RISET = 750Ω; KTERM × %IFAST-CHG,
where %IFAST-CHG is 5 to 10%		 174 199 224
IPRE-TERM Current for programming the term. and precharge with resistor. ITerm-Start is the initial PRE-TERM curent. RPRE-TERM = 2k, VOUT = 4.15V 71 75 81 μA
%TERM Termination current formula RTERM/ KTERM
ITerm-Start Elevated PRE-TERM current for, tTerm-Start, during start of charge to prevent recharge of full battery, 80 85 92 μA
RECHARGE OR REFRESH
VRCH Recharge detection threshold – Normal Temp VIN = 5V, VTS = 0.5V, VOUT: 4.25V → VRCH VO(REG)–0.120 VO(REG) –0.095 VO(REG)–0.070 V
Recharge detection threshold – Hot Temp VIN = 5V, VTS = 0.2V, VOUT: 4.15V → VRCH VO_HT(REG)–0.130 VO_HT(REG)–0.105 VO_HT(REG)–0.080 V
BATTERY DETECT ROUTINE(1)
VREG-BD VOUT Reduced regulation during battery detect VIN = 5V, VTS = 0.5V, Battery Absent VO(REG)–0.450 VO(REG–0.400 VO(REG)–0.350 V
IBD-SINK Sink current during VREG-BD

6

 10 mA
VBD-HI High battery detection threshold VIN = 5V, VTS = 0.5V, Battery Absent VO(REG)–0.150 VO(REG)–0.100 VO(REG)–0.050 V
VBD-LO Low battery detection threshold VIN = 5V, VTS = 0.5V, Battery Absent VREG-BD +0.050 VREG-BD +0.100 VREG-BD +0.150 V
BATTERY-PACK NTC MONITOR(2)
INTC-10k NTC bias current; 10k NTC thermistor, BQ24050 VTS = 0.3V 48 50 52 μA
INTC-100k NTC bias current; 100k NTC thermistor, BQ24052 VTS = 0.3V 4.8 5 5.2 μA
INTC-DIS-10k BQ24050 bias current when Charging is disabled. VTS = 0V 27 30 34 μA
INTC-DIS-100k BQ24052 bias current when Charging is disabled. VTS = 0V 4.4 5 5.8 μA
INTC-FLDBK-10k INTC is reduced prior to entering TTDM to keep cold thermistor from entering TTDM, BQ24050 VTS: Set to 1.525V 4 5 6.5 μA
INTC-FLDBK-100k INTC is reduced prior to entering TTDM to keep cold thermistor from entering TTDM, BQ24052 VTS: Set to 1.525V 1.1 1.5 1.9 μA
VTTDM(TS) Termination and timer disable mode Threshold – Enter VTS: 0.5V → 1.7V; Timer Held in Reset 1550 1600 1650 mV
VHYS-TTDM(TS) Hysteresis exiting TTDM VTS: 1.7V → 0.5V; Timer Enabled 100 mV
VCLAMP(TS) TS maximum voltage clamp VTS= Open (Float) 1800 1950 2000 mV
VTS_I-FLDBK TS voltage where INTC is reduce to keep thermistor from entering TTDM INTC adjustment (90 to 10%; 45 to 6.6uA) takes place near this spec threshold.
VTS: 1.425V → 1.525V		 1475 mV
CTS Optional Capacitance – ESD 0.22 μF
VTS-0°C BQ2405x Low temperature CHG Pending Low Temp Charging to Pending;

VTS: 1V → 1.5V		 1205 1230 1255 mV
VHYS-0°C Hysteresis at 0°C Charge pending to low temp charging;
VTS: 1.5V → 1V		 86 mV
VTS-10°C Low temperature, half charge Normal charging to low temp charging;
VTS: 0.5V → 1V		 765 790 815 mV
VHYS-10°C Hysteresis at 10°C Low temp charging to normal CHG;
VTS: 1V → 0.5V		 35 mV
VTS-45°C High temperature at 4.1V Normal charging to high temp CHG;
VTS: 0.5V → 0.2V		 263 278 293 mV
VHYS-45°C Hysteresis at 45°C High temp charging to normal CHG;
VTS: 0.2V → 0.5V		 10.7 mV
VTS-60°C High temperature Disable High temp charge to pending;
VTS: 0.2V → 0.1V		 170 178 186 mV
VHYS-60°C Hysteresis at 60°C Charge pending to high temp CHG;
VTS: 0.1V → 0.2V		 11.5 mV
VTS-EN-10k Charge Enable Threshold, (10k NTC) VTS: 0V → 0.175V; 80 88 96 mV
VTS-DIS_HYS-10k HYS below VTS-EN-10k to Disable, (10k NTC) VTS: 0.125V → 0V; 12 mV
VTS-EN-100k Charge Enable Threshold, (100k NTC) VTS: 0V → 0.175V 140 150 160 mV
VTS-DIS_HYS-100k HYS below VTS-EN-100k to Disable, (100k NTC) VTS: 0.125V → 0V; 50 mV
THERMAL REGULATION
TJ(REG) Temperature regulation limit 125 °C
TJ(OFF) Thermal shutdown temperature 155 °C
TJ(OFF-HYS) Thermal shutdown hysteresis 20 °C
LOGIC LEVELS ON ISET2
VIL Logic LOW input voltage Sink more than 8μA 0.4 V
VIH Logic HIGH input voltage Source more than 8μA 1.4 V
IIL Sink current required for LO 2 9 μA
IIH Source current required for HI 1.1

9.5

 μA
VFLT ISET2 Float Voltage 650 900 1200 mV
D+/D– DETECTION – BQ2405x
VD+ Bias at D+, during detection routine Can source at least 200μA 0.475 0.6 0.7 V
ID+ Current Limit at D+ pin, during detection routine VD+ = 0V 1.5 mA
ID– Current Sink at D– pin, during detection routine VD– = 0.5V 50 100 150 μA
ID+_LEAK D+ leakage when not in detection mode VD+ = 5V 1 μA
ID–_LEAK D– leakage when not in detection mode VD– = 5V 1 μA
VDPDM_0.4V D– Comparator Threshold Rising 0.35 0.45 V
VDPDM_HYS_0.4V D– Comparator Hysteresis 42 mV
VDPDM_0.8V D+/D– Comparator Threshold Rising 0.75 0.875 V
VDPDM_HYS_0.8V D+/D– Comparator Hysteresis 42 mV
LOGIC LEVELS ON CHG
VOL Output LOW voltage ISINK = 5mA 0.4 V
Ilkg Leakage current into IC V CHG = 5V 1 μA
(1) In Hot Mode VO(REG) becomes VO_HT(REG)
(2) TS pin: BQ24050: 10k NTC; BQ24052: 100k NTC; see Section 7.3.11 for thermistor information.