JAJSL99 August   2021 TPS1653

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Hot Plug-In and In-Rush Current Control
        1. 8.3.1.1 Thermal Regulation Loop
      2. 8.3.2  Undervoltage Lockout (UVLO)
      3. 8.3.3  Overload and Short Circuit Protection
        1. 8.3.3.1 Overload Protection
        2. 8.3.3.2 Short Circuit Protection
          1. 8.3.3.2.1 Start-Up With Short-Circuit On Output
      4. 8.3.4  Current Monitoring Output (IMON)
      5. 8.3.5  FAULT Response (FLT)
      6. 8.3.6  Power Good Output (PGOOD)
      7. 8.3.7  IN, P_IN, OUT and GND Pins
      8. 8.3.8  Thermal Shutdown
      9. 8.3.9  Low Current Shutdown Control (SHDN)
      10. 8.3.10 Enable Input (EN)
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Programming the Current-Limit Threshold R(ILIM) Selection
        2. 9.2.2.2 Undervoltage Lockout and Overvoltage Set Point
        3. 9.2.2.3 Setting Output Voltage Ramp Time (tdVdT)
          1. 9.2.2.3.1 Support Component Selections RPGOOD and C(IN)
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 48-V Power Amplifier Protection for Telecom Radios
  10. 10Power Supply Recommendations
    1. 10.1 Transient Protection
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

GUID-20210222-CA0I-WPKD-BNXC-W1R08BDCTV5B-low.gifFigure 5-1 TPS16530 RGE Package24-Pin VQFNTop View
GUID-20210219-CA0I-FJTJ-JJ0G-XLKKZXFCG9FH-low.gifFigure 5-2 TPS16530 PWP Package20-Pin HTSSOPTop View
Table 5-1 Pin Functions
PIN TYPE DESCRIPTION
NAME TPS16530
VQFN HTSSOP
IN 1 1 P Power Input. Connects to the DRAIN of the internal FET.
2 2
— 3
P_IN 5 4 P Supply voltage of the device. Always connect P_IN to IN directly.
UVLO 6 6 I Input for setting the programmable undervoltage lockout threshold. An undervoltage event turns off the internal FET and asserts FLT to indicate the power-failure. If not used, this pin can be connected to IN or P_IN.
EN 7 8 I Active low enable pin. If not used, this pin can be connected to GND. Do not leave this pin open or floating.
GND 8 9 — Connect GND to system ground
dVdT 9 10 I/O A capacitor from this pin to GND sets output voltage slew rate. Leaving this pin floating enables device power up in thermal regulation resulting in fast output charge. See the Hot Pug-In and In-Rush Current Control section.
ILIM 10 11 I/O A resistor from this pin to GND sets the overload limit. See Overload and Short Circuit Protection section.
MODE 11 12 I Mode selection pin for Overload fault response. See the Device Functional Modes section.
SHDN 12 13 I Shutdown pin. Pulling SHDN low makes the device to enter into low power shutdown mode. Cycling SHDN pin voltage resets the device that has latched off due to a fault condition.
IMON 13 14 O Analog current monitor output. This pin sources a scaled down ratio of current through the internal FET. A resistor from this pin to GND converts current to proportional voltage. If unused, leave this pin floating.
FLT 14 15 O Fault event indicator. It is an open drain output. If unused, leave floating or connect to GND.
PGOOD 16 16 O Active High. A high indicates that the internal FET is enhanced. PGOOD goes low when the internal FET is turned OFF during a fault or when SHDN is pulled low. If PGOOD is unused then connect to GND or leave it floating.
OUT 17 18 P Power Output of the device
18 19
— 20
N.C 3 5 — Internally Not connected. Can be connected to other pins (P_IN, OUT, GND) for enhanced thermal performance.
4 7
15 17
19 —
20 —
21 —
22 —
23 —
24 —
PowerPAD™ — Connect the PowerPAD to GND plane for heat sinking. Do not use the PowerPAD as the only electrical connection to GND.