JAJSLC6 November   2021 UCC28781-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Detailed Pin Description
      1. 7.3.1  BUR Pin (Programmable Burst Mode)
      2. 7.3.2  FB Pin (Feedback Pin)
      3. 7.3.3  REF Pin (Internal 5-V Bias)
      4. 7.3.4  VDD Pin (Device Bias Supply)
      5. 7.3.5  P13 and SWS Pins
      6. 7.3.6  S13 Pin
      7. 7.3.7  IPC Pin (Intelligent Power Control Pin)
      8. 7.3.8  RUN Pin (Driver and Bias Source for Isolator)
      9. 7.3.9  PWMH and AGND Pins
      10. 7.3.10 PWML and PGND Pins
      11. 7.3.11 SET Pin
      12. 7.3.12 RTZ Pin (Sets Delay for Transition Time to Zero)
      13. 7.3.13 RDM Pin (Sets Synthesized Demagnetization Time for ZVS Tuning)
      14. 7.3.14 XCD Pin
      15. 7.3.15 CS, VS, and FLT Pins
    4. 7.4 Device Functional Modes
      1. 7.4.1  Adaptive ZVS Control with Auto-Tuning
      2. 7.4.2  Dead-Time Optimization
      3. 7.4.3  EMI Dither and Dither Fading Function
      4. 7.4.4  Control Law Across Entire Load Range
      5. 7.4.5  Adaptive Amplitude Modulation (AAM)
      6. 7.4.6  Adaptive Burst Mode (ABM)
      7. 7.4.7  Low Power Mode (LPM)
      8. 7.4.8  First Standby Power Mode (SBP1)
      9. 7.4.9  Second Standby Power Mode (SBP2)
      10. 7.4.10 Startup Sequence
      11. 7.4.11 Survival Mode of VDD (INT_STOP)
      12. 7.4.12 System Fault Protections
        1. 7.4.12.1  Brown-In and Brown-Out
        2. 7.4.12.2  Output Over-Voltage Protection (OVP)
        3. 7.4.12.3  Input Over Voltage Protection (IOVP)
        4. 7.4.12.4  Over-Temperature Protection (OTP) on FLT Pin
        5. 7.4.12.5  Over-Temperature Protection (OTP) on CS Pin
        6. 7.4.12.6  Programmable Over-Power Protection (OPP)
        7. 7.4.12.7  Peak Power Limit (PPL)
        8. 7.4.12.8  Output Short-Circuit Protection (SCP)
        9. 7.4.12.9  Over-Current Protection (OCP)
        10. 7.4.12.10 External Shutdown
        11. 7.4.12.11 Internal Thermal Shutdown
      13. 7.4.13 Pin Open/Short Protections
        1. 7.4.13.1 Protections on CS pin Fault
        2. 7.4.13.2 Protections on P13 pin Fault
        3. 7.4.13.3 Protections on RDM and RTZ pin Faults
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application Circuit
      1. 8.2.1 Design Requirements for a 60-W, 15-V ZVSF Bias Supply Application with a DC Input
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Bulk Capacitance and Minimum Bulk Voltage
        2. 8.2.2.2 Transformer Calculations
          1. 8.2.2.2.1 Primary-to-Secondary Turns Ratio (NPS)
          2. 8.2.2.2.2 Primary Magnetizing Inductance (LM)
          3. 8.2.2.2.3 Primary Winding Turns (NP)
          4. 8.2.2.2.4 Secondary Winding Turns (NS)
          5. 8.2.2.2.5 Auxiliary Winding Turns (NA)
          6. 8.2.2.2.6 Winding and Magnetic Core Materials
        3. 8.2.2.3 Calculation of ZVS Sensing Network
        4. 8.2.2.4 Calculation of BUR Pin Resistances
        5. 8.2.2.5 Calculation of Compensation Network
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1  General Considerations
      2. 10.1.2  RDM and RTZ Pins
      3. 10.1.3  SWS Pin
      4. 10.1.4  VS Pin
      5. 10.1.5  BUR Pin
      6. 10.1.6  FB Pin
      7. 10.1.7  CS Pin
      8. 10.1.8  AGND Pin
      9. 10.1.9  PGND Pin
      10. 10.1.10 Thermal Pad
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Receiving Notification of Documentation Updates
    2. 11.2 サポート・リソース
    3. 11.3 Trademarks
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 用語集
  12. 12Mechanical, Packaging, and Orderable Information

7.4.6 Adaptive Burst Mode (ABM)

As the load current reduces to IO(BUR) where VCS reaches the VCST(BUR) threshold, the control mode transitions to ABM starts and VCS is clamped. The peak magnetizing current and the switching frequency (fSW) of each switching cycle are fixed for a given input voltage level. VCST(BUR) is programmed by the BUR pin voltage (VBUR). The PWM pattern of ABM is shown in #T4924628-34. When RUN goes high, a delay time between RUN and PWML (tD(RUN-PWML)) is given to allow both the gate driver and the UCC28781-Q1 controller time to wake up from a wait state to a run state. The first PWML pulse turns on QL close to a valley point of the DCM ringing on the switch-node voltage (VSW) by sensing the condition of zero crossing detection (ZCD) on the auxiliary winding voltage (VAUX).

The following switching cycles operate in a ZVS condition, since PWMH is enabled. As the number of PWML pulses (NSW) in the burst packet reaches its target value, the RUN pin pulls low after the ZCD of the last switching cycle is detected, and forces the isolated gate driver and controller into a wait state for the quiescent current reduction of both devices. In this mode, the minimum off-time of the RUN signal is 2.2 µs and the minimum on-time of PWML is limited to the leading-edge blanking time (tCSLEB) of the peak current loop. However, more grouped pulses means more risk of higher output ripple and higher audible noise. The following equation estimates how burst frequency (fBUR) varies with output load and other parameters.

Equation 12. f B U R = I O I O ( B U R ) × f S W N S W

As IO < IO(BUR), fBUR can become lower than the audible noise range if NSW is fixed. In ABM, NSW is modulated to ensure fBUR stays above 20 kHz by monitoring fBUR in each burst period. As IO decreases, fBUR decreases and reaches a predetermined low-level frequency threshold (fBUR(LR)) of 25 kHz. The ABM loop commands Nsw of both PWML and PWMH to be reduced by one pulse to maintain fBUR above fBUR(LR). At the same time, the burst frequency ripple on the output voltage reduces as NSW drops with the load reduction. As IO increases, fBUR becomes higher and reaches a predetermined high-level frequency threshold (fBUR(UP)). The ABM loop commands NSW to be increased by one pulse to push fBUR back below fBUR(UP).

The maximum NSW and the fBUR(UP) thresholds are modified based on the output voltage condition, i.e., the positive VS-pin voltage level. When the VVS sampled at the PWMH falling edge is less than the 2.4-V threshold (VVSLV(LR)), the maximum NSW is 5 pulses and the fBUR(UP2) is 50 kHz. When the sampled VVS is higher than the 2.5-V threshold (VVSLV(UP)), the maximum NSW is 9 pulses, the fBUR(UP2) is 50 kHz for NSW ≤ 3, and the fBUR(UP1) is 34 kHz for NSW> 3. The IPC-pin voltage does not affect the parameters in ABM mode.

This algorithm maximizes the number of pulses in each burst packet to improve light-load efficiency, while also limiting the burst output ripple and audible noise. As IO is close to the boundary between AAM and ABM, the two burst packets with the maximum pulse count may start to bundle together. In order to mitigate the output ripple and audible noise concerns, when the bundled burst packet appears two times within eight sequential burst cycles, the 5-µA current sink into the BUR pin is enabled to reduce VBUR . The less energy per cycle with a lower VBURwill force the control loop to transition from ABM to AAM smoothly in order to allow the peak current increase to maintain the output voltage regulation.

GUID-44FDA946-CD6B-4A1A-8A63-C6030B63FE53-low.gifFigure 7-31 PWM Pattern in ABM