JAJSLF9B December   2015  – March 2021 LMR16030

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency Peak Current Mode Control
      2. 7.3.2  Slope Compensation
      3. 7.3.3  Sleep Mode
      4. 7.3.4  Low Dropout Operation and Bootstrap Voltage (BOOT)
      5. 7.3.5  Adjustable Output Voltage
      6. 7.3.6  Enable and Adjustable Undervoltage Lockout
      7. 7.3.7  External Soft Start
      8. 7.3.8  Switching Frequency and Synchronization (RT/SYNC)
      9. 7.3.9  Power Good (PGOOD)
      10. 7.3.10 Overcurrent and Short Circuit Protection
      11. 7.3.11 Overvoltage Protection
      12. 7.3.12 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Active Mode
      3. 7.4.3 CCM Mode
      4. 7.4.4 Light Load Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Output Voltage Set-Point
        3. 8.2.2.3 Switching Frequency
        4. 8.2.2.4 Output Inductor Selection
        5. 8.2.2.5 Output Capacitor Selection
        6. 8.2.2.6 Schottky Diode Selection
        7. 8.2.2.7 Input Capacitor Selection
        8. 8.2.2.8 Bootstrap Capacitor Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
        1. 11.1.2.1 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  12. 12Mechanical, Packaging, and Orderable Information

7.3.9 Power Good (PGOOD)

The LMR16030P has a built-in power-good flag shown on PGOOD pin to indicate whether the output voltage is within its regulation level. The PGOOD signal can be used for start-up sequencing of multiple rails or fault protection. The PGOOD pin is an open-drain output that requires a pullup resistor to an appropriate DC voltage. Voltage seen by the PGOOD pin should never exceed 7 V. A resistor divider pair can be used to divide the voltage down from a higher potential. A typical range of pullup resistor value is 10 kΩ to 100 kΩ.

Refer to Figure 7-9. When the FB voltage is within the power-good band, +7% above and -6% below the internal reference VREF typically, the PGOOD switch is turned off and the PGOOD voltage is pulled up to the voltage level defined by the pullup resistor or divider. When the FB voltage is outside of the tolerance band, +9% above or -8% below VREF typically, the PGOOD switch is turned on and the PGOOD pin voltage is pulled low to indicate power bad.

GUID-DAEA3062-78F8-479F-B959-8F83A7053C37-low.gifFigure 7-9 Power-Good Flag