JAJSLF9B December   2015  – March 2021 LMR16030

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency Peak Current Mode Control
      2. 7.3.2  Slope Compensation
      3. 7.3.3  Sleep Mode
      4. 7.3.4  Low Dropout Operation and Bootstrap Voltage (BOOT)
      5. 7.3.5  Adjustable Output Voltage
      6. 7.3.6  Enable and Adjustable Undervoltage Lockout
      7. 7.3.7  External Soft Start
      8. 7.3.8  Switching Frequency and Synchronization (RT/SYNC)
      9. 7.3.9  Power Good (PGOOD)
      10. 7.3.10 Overcurrent and Short Circuit Protection
      11. 7.3.11 Overvoltage Protection
      12. 7.3.12 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Active Mode
      3. 7.4.3 CCM Mode
      4. 7.4.4 Light Load Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Output Voltage Set-Point
        3. 8.2.2.3 Switching Frequency
        4. 8.2.2.4 Output Inductor Selection
        5. 8.2.2.5 Output Capacitor Selection
        6. 8.2.2.6 Schottky Diode Selection
        7. 8.2.2.7 Input Capacitor Selection
        8. 8.2.2.8 Bootstrap Capacitor Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
        1. 11.1.2.1 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  12. 12Mechanical, Packaging, and Orderable Information

7.3.6 Enable and Adjustable Undervoltage Lockout

The LMR16030 is enabled when the VIN pin voltage rises above 4.0 V (typical) and the EN pin voltage exceeds the enable threshold of 1.2 V (typical). The LMR16030 is disabled when the VIN pin voltage falls below 3.715 V (typical) or when the EN pin voltage is below 1.2 V. The EN pin has an internal pullup current source (typically IEN = 1 μA) that enables operation of the LMR16030 when the EN pin is floating.

Many applications will benefit from the employment of an enable divider RENT and RENB in Figure 7-3 to establish a precision system UVLO level for the stage. System UVLO can be used for supplies operating from utility power as well as battery power. It can be used for sequencing, ensuring reliable operation, or supply protection, such as a battery. An external logic signal can also be used to drive EN input for system sequencing and protection.

When EN terminal voltage exceeds 1.2 V, an additional hysteresis current (typically IHYS = 3.6 μA) is sourced out of EN terminal. When the EN terminal is pulled below 1.2 V, IHYS current is removed. This additional current facilitates adjustable input voltage UVLO hysteresis. Use Equation 2 and Equation 3 to calculate RENT and RENB for desired UVLO hysteresis voltage.

GUID-F6FBEE4D-FDF6-48EF-B301-EBF497B18889-low.gifFigure 7-3 System UVLO By Enable Dividers
Equation 2. GUID-863DB7B8-22C5-4334-AE00-C7B27E1CDED8-low.gif
Equation 3. GUID-0BDF5719-4D2E-4552-8D23-1B52374C3080-low.gif

where VSTART is the desired voltage threshold to enable LMR16030, VSTOP is the desired voltage threshold to disable device, IEN = 1 μA and IHYS = 3.6 μA typically.