JAJSLJ6C november   2020  – august 2023 UCC25800-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Management
      2. 8.3.2 Oscillator
      3. 8.3.3 External Synchronization
      4. 8.3.4 Dead-Time
        1. 8.3.4.1 Adaptive Dead-time
        2. 8.3.4.2 Maximum Programmable Dead-time
      5. 8.3.5 Protections
        1. 8.3.5.1 Overcurrent Protection
          1. 8.3.5.1.1 OCP Threshold Setting
          2. 8.3.5.1.2 Output Power Capability
        2. 8.3.5.2 Input Overvoltage Protection (OVP)
        3. 8.3.5.3 Over-Temperature Protection (TSD)
        4. 8.3.5.4 Pin-Fault Protections
        5. 8.3.5.5 VREG Pin Protection
      6. 8.3.6 DIS/FLT Pin operation
        1. 8.3.6.1 FAULT Codes
    4. 8.4 Device Functional Modes
      1. 8.4.1 UVLO Mode
      2. 8.4.2 Soft-start Mode
      3. 8.4.3 Normal Operation Mode
      4. 8.4.4 Disabled Mode
      5. 8.4.5 Fault Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 LLC Converter Operation Principle
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
    3. 9.3 What to Do and What Not to Do
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 用語集
  14. 13Mechanical, Packaging, and Orderable Information
8.3.5.1.1 OCP Threshold Setting

The UCC25800-Q1 transformer driver can support 6-W output power with 24-V input. For designs with lower power levels, the overcurrent protection (OCP) threshold can be adjusted accordingly to limit the maximum output power to improve the system reliability.

The OCP threshold setting shares the same pin as the maximum dead-time programming through OC/DT pin. During the transformer driver start-up sequence (after its VREG pin settles down to its final value) an internal 50-µA current source flowing out of OC/DT pin is turned on and off. The voltage on the OC/DT pin is measured at the current source on and off conditions. The measured voltage difference is used to set the OCP threshold. After the OCP setting is determined, the current source is turned off, so that the voltage on the OC/DT pin can be used for the maximum dead-time setting.

GUID-20211104-SS0I-2QKM-JQVN-85XK67HV6J0C-low.svgFigure 8-12 Current Source On
GUID-20211104-SS0I-V8RW-FHTJ-WDNCWQG6R9LZ-low.svgFigure 8-13 Current Source Off

According to the Thevenin theorem, the measured voltage difference is the current source multiplied by the Thevenin resistance on the voltage divider on OC/DT pin. The OCP settings using different Thevenin resistance are summarized in Table 8-1. The Thevenin resistance can be calculated using Equation 5.

Equation 5. R t h = R a   × R b R a + R b
Table 8-1 OCP Settings
OCP1 _1 OCP1_2 OCP1_3 OCP1_4 OCP1_5 OCP1_6
Rth 22.25 kΩ ~ 23.15 kΩ 16.4 kΩ ~ 17 kΩ 11.7 kΩ ~ 12.1 kΩ 7.95 kΩ ~ 8.25 kΩ 4.9 kΩ ~ 5.1 kΩ 2.45 kΩ ~ 2.55 kΩ
OCP1 threshold (IOCP) 1/6 IOCP1max 1/3 IOCP1max 1/2 IOCP1max 2/3 IOCP1max 5/6 IOCP1max IOCP1max
OCP2 threshold during soft-start 5 A 5 A 5 A 5 A 5 A 5 A
OCP2 threshold after soft-start 5/6 IOCP1max 5/3 IOCP1max 5/2 IOCP1max 10/3 IOCP1max 25/6 IOCP1max 5 IOCP1max

To ensure accurate reading of the Thevenin resistance, the time constant of Rth and any capacitance connected to the OC/DT pin should not be greater than 20 µs. For this reason, the maximum recommended capacitance on the pin is 1 nF. It is not required to add capacitance to the pin.

The OC/DT pin voltage during start-up is illustrated in Figure 8-14.

GUID-20211104-SS0I-HHDD-XWGZ-0TN0SFXFL4GW-low.svg Figure 8-14 OC/DT pin voltage during start-up
A.
Equation 6. V = V R E G × R b R a + R b
B.
Equation 7. ∆ V = 50   µ A × R t h