JAJSLJ6C november 2020 – august 2023 UCC25800-Q1
PRODUCTION DATA
The DIS/FLT pin is an input/output pin. It can be
Internally the pin is tied high through a 100-kΩ pullup resistor from VREG. This pullup resistor activates only after the VREG pin is high. If the UCC25800-Q1 transformer driver enters the fault mode, the DIS/FLT pin is pulled low internally via a 750-µA current source. When the pin is low, switching is inhibited.
The DIS/FLT internal pulldown current source is activated during the power-up sequence once the VCC voltage exceeds the UVLO rising threshold. After the VREG voltage has risen above the VREGOK threshold, the pulldown current source is released and the DIS/FLT pin rises (unless it is externally pulled down). When the DIS/FLT pin voltage exceeds the ENTH threshold, the transformer driver is enabled. When DIS/FLT pin falls below the DISTH the transformer driver is disabled. When the transformer driver is disabled its power consumption is reduced to IVCCDIS.
If there is concern about noise coupling to the DIS/FLT pin it can be pulled up with an external resistor to an external rail or to VREG. In order to read the pin as a status flag, the external resistor value must be high enough that the 750-µA current source can pull the pin below the threshold level of the device reading the pin. It is recommended that the value for an external pullup resistor to 5 V is 10 kΩ and the value for an external pullup resistor to 3.3 V is 4.7 kΩ in order for the pin to be read as a fault output.
If the DIS/FLT pin functionality is not required, it can be left floating or tied to VREG to allow the transformer driver to operate normally.