JAJSLJ6C november   2020  – august 2023 UCC25800-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Management
      2. 8.3.2 Oscillator
      3. 8.3.3 External Synchronization
      4. 8.3.4 Dead-Time
        1. 8.3.4.1 Adaptive Dead-time
        2. 8.3.4.2 Maximum Programmable Dead-time
      5. 8.3.5 Protections
        1. 8.3.5.1 Overcurrent Protection
          1. 8.3.5.1.1 OCP Threshold Setting
          2. 8.3.5.1.2 Output Power Capability
        2. 8.3.5.2 Input Overvoltage Protection (OVP)
        3. 8.3.5.3 Over-Temperature Protection (TSD)
        4. 8.3.5.4 Pin-Fault Protections
        5. 8.3.5.5 VREG Pin Protection
      6. 8.3.6 DIS/FLT Pin operation
        1. 8.3.6.1 FAULT Codes
    4. 8.4 Device Functional Modes
      1. 8.4.1 UVLO Mode
      2. 8.4.2 Soft-start Mode
      3. 8.4.3 Normal Operation Mode
      4. 8.4.4 Disabled Mode
      5. 8.4.5 Fault Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 LLC Converter Operation Principle
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
    3. 9.3 What to Do and What Not to Do
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 用語集
  14. 13Mechanical, Packaging, and Orderable Information

7.5 Electrical Characteristics

Unless otherwise stated: VVCC = 15 V, RRT = open, CVREG = 470 nF, and -40 °C <TJ =TA < 125 °C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE
UVLOR VCC turn on threshold VCC rising 8 8.6 9 V
UVLOF VCC turn off threshold VCC falling 7.5 8 8.5 V
OVSD VCC overvoltage shutdown threshold VCC rising 35 37 39 V
OVRS VCC overvoltage reset VCC falling 34 36 38 V
OVBLNK Overvoltage blanking time VVCC = 40 V 0.75 1.3 2 µs
SUPPLY CURRENT
IVCCUVLO VCC current during UVLO VVCC = 7.5 V 200 500 µA
IVCCRUN Input current, not including FET current (3) fSW = 1.2 MHz, DIS/FLT = 1, SW open, IVREG = 0 mA, VCC = 12 V 14 20 mA
IVCCDIS Supply current when disabled No switching, DIS/FLT = 0, IVREG = 0 mA 660 800 µA
VREG OUTPUT
VREG Internal regulated reference IVREG = 0 mA, DIS/FLT = 0 4.75 5 5.25 V
VREGLINE Line Regulation IVREG = 0 mA, 9 V ≤ VVCC ≤ 34 V 10 mV
VREGLOAD Load Regulation 0 mA ≤ IVREG ≤ 1 mA -100 mV
VREGOK Threshold for VREG GOOD VREG rising 4.05 4.5 4.95 V
VREGLOW VREG fault threshold VREG falling 3.6 4 4.4 V
MOSFETs
RDSON On Resistance PMOS ISW = -500 mA 0.45 0.75 Ω
NMOS ISW = +500 mA 0.3 0.5 Ω
OSCILLATOR
fSW SW switching frequency VRT = 0.25 V 94 100 106 kHz
VRT = 2.5 V 0.94 1 1.06 MHz
Default switching frequency, RT open 1.128 1.2 1.272 MHz
fSWtol Tolerance 10 kΩ ≤ RRT ≤ 100 kΩ 94 106 %
Duty Duty cycle RT open 49 50 51 %
RTSHORT Short circuit fault theshold 130 150 170 mV
RTOPEN Open-circuit default fOSC threshold 2.9 3 3.1 V
SYNC
SYNCRISNG SYNC rising threshold VSYNC rising 2.0 2.2 2.4 V
SYNCFALLING SYNC falling threshold VSYNC falling 1.53 1.7 1.87 V
ADAPTIVE DEAD-TIME
DT_HSTH High-side dead-time detection threshold with respect to VCC SW rising -1.2 -1 -0.8 V
DT_LSTH Low-side dead-time detection threshold SW falling 0.8 1 1.2 V
DT_HSDELAY High-side turn on delay From SW crossing DT_HSTH to HS turning on 20 45 ns
DT_LSDELAY Low-side turn on delay From SW crossing DT_LSTH to LS turning on 20 45 ns
PROGRAMMABLE MAXIMUM DEAD-TIME
OC/DTSHORT short threshold for OC/DT pin 450 500 550 mV
OC/DTOPEN open threshold for OC/DT pin 4.3 4.5 4.7 V
DTMAX Programmable maximum dead-time VOC/DT = 3.9 V 45 50 55 ns
VOC/DT = 1.9 V 135 150 165 ns
OVER-CURRENT PROTECTION
IOCP1max First level maximum OCP setting threshold Low side only 0.9 1 1.1 A
OCP1TO OCP1 time out Peak current exceeds threshold time out to trigger OCP1 fault 1.9 2.1 2.3 ms
IOCP2max Second level maximum OCP threshold Low side and high side 4.25 5 5.75 A
OCP2FILTER OCP2 filter time Continuous over-current to trigger OCP2 fault, low side and high side 80 100 120 ns
OVER-TEMPERATURE PROTECTION
TSD Thermal shutdown threshold TJ = TA(1) 160 °C
THYST Hysteresis TJ = TA (1) 20 °C
ENABLE_DISABLE FUNCTION
ENTH Enable threshold DIS/FLT rising 2 2.2 2.4 V
DISTH Disable threshold DIS/FLT falling 1.53 1.7 1.87 V
Ipd_DIS Internal pull down disable current VDIS/FLT = 5 V 650 750 850 μA
RESTARTDEL Restart delay after fault (2) 100 ms
(1) Specified by design. No production tested.
(2) Specified by bench characterization. No production tested.
(3) This current includes the SW pin parasitic capaticor charge and discharge current. When operating with LLC, soft switching removes the capacitor charge and discharge current. Actual current is smaller.