JAJSLJ8 March   2021 TPSM13604H

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 COT Control Circuit Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Overvoltage Comparator
      2. 7.3.2 Current Limit
      3. 7.3.3 Thermal Protection
      4. 7.3.4 Zero Coil Current Detection
      5. 7.3.5 Prebiased Start-up
    4. 7.4 Device Functional Modes
      1. 7.4.1 Discontinuous Conduction and Continuous Conduction Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Design Steps for the TPSM13604 Application
          1. 8.2.2.1.1 Enable Divider, RENT, and RENB Selection
          2. 8.2.2.1.2 Output Voltage Selection
          3. 8.2.2.1.3 Soft-Start Capacitor, CSS, Selection
          4. 8.2.2.1.4 Output Capacitor, CO, Selection
            1. 8.2.2.1.4.1 Capacitance
            2. 8.2.2.1.4.2 ESR
          5. 8.2.2.1.5 Input Capacitor, CIN, Selection
          6. 8.2.2.1.6 ON-Time, RON, Resistor Selection
            1. 8.2.2.1.6.1 Discontinuous Conduction and Continuous Conduction Mode Selection
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Power Module SMT Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Power Dissipation and Board Thermal Requirements
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 用語集
    7. 11.7 静電気放電に関する注意事項
  12. 12Mechanical, Packaging, and Orderable Information

10.1 Layout Guidelines

PCB layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage drop in the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability. Good layout can be implemented by following a few simple design rules.

  1. Minimize the area of switched current loops.

    From an EMI reduction standpoint, it is imperative to minimize the high di/dt paths during PCB layout. The high current loops that do not overlap have high di/dt content that cause observable high frequency noise on the output pin if the input capacitor (Cin1) is placed at a distance away from the TPSM13604. Therefore, place CIN1 as close as possible to the TPSM13604 VIN and GND exposed pad. This minimizes the high di/dt area and reduce radiated EMI. Additionally, grounding for both the input and output capacitor must consist of a localized top-side plane that connects to the GND exposed pad (EP).

  2. Have a single point ground.

    The ground connections for the feedback, soft start, and enable components should be routed to the GND pin of the device. This prevents any switched or load currents from flowing in the analog ground traces. If not properly handled, poor grounding can result in degraded load regulation or erratic output voltage ripple behavior. Provide the single point ground connection from pin 4 to EP.

  3. Minimize trace length to the FB pin.

    Both feedback resistors, RFBT and RFBB, and the feedforward capacitor, CFF, must be close to the FB pin. Since the FB node is high impedance, maintain the copper area as small as possible. The trace are from RFBT, RFBB, and CFF must be routed away from the body of the TPSM13604 to minimize noise.

  4. Make input and output bus connections as wide as possible.

    This reduces any voltage drops on the input or output of the converter and maximizes efficiency. To optimize voltage accuracy at the load, ensure that a separate feedback voltage sense trace is made to the load. Doing so corrects for voltage drops and provide optimum output accuracy.

  5. Provide adequate device heat-sinking.

    Use an array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom PCB layer. If the PCB has a plurality of copper layers, these thermal vias can also be employed to make connection to inner layer heat-spreading ground planes. For best results use a 6 × 6 via array with minimum via diameter of 8 mils thermal vias spaced 59 mils (1.5 mm). Ensure enough copper area is used for heat-sinking to keep the junction temperature below 125°C.