JAJSLK0B march 2021 – june 2023 TMUX7462F
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | TA | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
ANALOG SWITCH | |||||||
VT | Threshold voltage for fault detector | 25°C | 0.7 | V | |||
LOGIC INPUT/ OUTPUT | |||||||
VIH | High-level input voltage | DR pin | –40°C to +125°C | 1.3 | V | ||
VIL | Low-level input voltage | DR pin | –40°C to +125°C | 0.8 | V | ||
IIH | High-level input current | VDR = logic high | –40°C to +125°C | 0.4 | 3 | µA | |
IIL | Low-level input current | VDR = logic low | –40°C to +125°C | –1 | –0.65 | µA | |
VOL(FLAG) | Low-level output voltage | FF pin, IO = 5 mA | –40°C to +125°C | 0.35 | V | ||
POWER SUPPLY | |||||||
VUVLO | Undervoltage lockout (UVLO) threshold voltage (VDD – VSS) | Rising edge, single supply | –40°C to +125°C | 5.1 | 5.8 | 6.4 | V |
Falling edge, single supply | –40°C to +125°C | 5 | 5.7 | 6.3 | V | ||
VHYS | VDD Undervoltage lockout (UVLO) hysteresis | Single supply | –40°C to +125°C | 0.2 | V | ||
RD(OVP) | Drain resistance to fault supply during overvoltage protection when enabled by DR pin |
25°C | 40 | kΩ |