JAJSMH7D April   2020  – May 2024 UCC27624

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Operating Supply Current
      2. 6.3.2 Input Stage
      3. 6.3.3 Enable Function
      4. 6.3.4 Output Stage
      5. 6.3.5 Low Propagation Delays and Tightly Matched Outputs
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 VDD and Undervoltage Lockout
        2. 7.2.2.2 Drive Current and Power Dissipation
      3. 7.2.3 Application Curves
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
    3. 9.3 Thermal Considerations
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 サード・パーティ製品に関する免責事項
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

6.1 Overview

The UCC27624 device represents TI's latest generation of dual-channel, low-side, high-speed, gate driver devices featuring 5-A source and sink current capability, fast switching characteristics, and a host of other features. UCC27624 Features and Benefits details the advantages of the gate driver's features, which combine to ensure efficient, robust, and reliable operation in high-frequency switching power circuits. The robust inputs of UCC27624 can handle –10 V, ensuring reliable operation in noisy environments. The driver has good transient handling capability on its output due to its reverse current handling, as well as rail-to-rail output drive, and a small propagation delay (typically 17 ns). With this built-in robustness, the UCC27624 device can also be directly connected to a gate drive transformer.

The input threshold of UCC27624 is compatible with TTL low-voltage logic, which is fixed and independent of VDD supply voltage. The driver can also work with CMOS-based controllers as long as the threshold requirement is met. The 1-V typical hysteresis offers excellent noise immunity.

Each channel has an enable pin, ENx, with a fixed TTL compatible threshold. The ENx pins are internally pulled up. Pulling ENx low disables the corresponding channel, while leaving ENx open provides normal operation. The ENx pins can be used as an additional input with the same performance as the INx pins.

Table 6-1 UCC27624 Features and Benefits
FEATURE BENEFIT
–10-V IN and EN capability Enhanced signal reliability and device robustness in noisy environments that experience ground bounce on the gate driver
17-ns (typical) propagation delay Extremely low-pulse transmission distortion
1-ns (typical) delay matching between channels Ease of paralleling outputs for higher (two times) current capability. This helps when driving parallel-power switches.
Expanded VDD operating range of 4.5 V to 26 V Flexibility in system design. Covers a wide range of power switches
Expanded operating temperature range of –40°C to +150°C Flexibility in system design. System robustness improvement
VDD UVLO protection Outputs are held low in UVLO condition, which ensures predictable, glitch-free operation at power-up and power-down.
Outputs are held low when input pins (INx) are in floating condition. Protection feature, especially useful in passing abnormal condition tests during safety certification
Outputs are enabled when enable pins (ENx) are in floating condition. Pin-to-pin compatibility with legacy devices from Texas Instruments in designs where Pin 1 and Pin 8 are "No Connect" pins
Input and enable threshold with wide hysteresis Enhanced noise immunity while retaining compatibility with microcontroller logic-level input signals (3.3 V, 5 V) optimized for digital power
Inputs independent of VDD System simplification, especially related to auxiliary bias supply architecture