JAJSMY4C September   2021  – December 2022 UCC14240-Q1

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Electrical Characteristics
    9. 6.9  Safety Limiting Values
    10. 6.10 Insulation Characteristics
    11. 6.11 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Stage Operation
        1. 7.3.1.1 VDD-VEE Voltage Regulation
        2. 7.3.1.2 COM-VEE Voltage Regulation
        3. 7.3.1.3 Power Handling Capability
      2. 7.3.2 Output Voltage Soft Start
      3. 7.3.3 ENA and PG
      4. 7.3.4 Protection Functions
        1. 7.3.4.1 Input Undervoltage Lockout
        2. 7.3.4.2 Input Overvoltage Lockout
        3. 7.3.4.3 Output Overvoltage Protection
        4. 7.3.4.4 Overpower Protection
          1. 7.3.4.4.1 Output Undervoltage Protection
        5. 7.3.4.5 Overtemperature Protection
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Capacitor Selection
        2. 8.2.2.2 RLIM Resistor Selection
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  9. Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  10. 10Mechanical, Packaging, and Orderable Information

Output Voltage Soft Start

UCC14240-Q1 power-up diagram of two output rails with soft start is shown in Figure 7-5. After VVIN > VVIN_UVLOP and ENA is pulled high, the soft-start sequence starts with burst duty cycle control with soft duty cycle increment. The burst duty cycle gradually increases from 12.5% to 50% over time by the primary-side control signal (DSS_PRI), so both VVDD-VEE and VCOM-VEE increase ratiometrically with a controlled shallow rising slope. When VVDD-VEE is increased above VVDD_UVLOS, there is a sufficient bias voltage for the feedback-loop communication channel, so the burst feedback control on the secondary side takes over. As a result, the DSS_PRI is pulled high and does not affect burst duty cycle anymore. The burst duty cycle is determined by comparing VFBVDD and VREF. VREF increases from 1.1V to 2.5 V with seven increment steps, where each 0.2-V step lasts 128 µs. After VVDD-VEE > VVDD_UVP, /PG is pulled low and the RLIM source-sink regulator for VCOM-VEE is enabled. The polarity of source or sink current of RLIM pin is determined by comparing VFBVEE and VREF so as to keep VCOM-VEE in tight regulation. The soft-start feature greatly reduces the input inrush current during power-up. In addition, if VVDD-VEE cannot reach to VVDD_UVLOS within 16 ms, then the device shuts down in a safe-state. The 16-ms soft-start time-out protects the module under output short circuit condition before power up.

Figure 7-5 Output voltage Soft-Start Diagram