The ENA input pin and PG output pin on the primary-side use 5-V TTL and 3.3-V LVTTL level logic thresholds.

The active-high enable input (ENA) pin is used to turn-on the isolated DC/DC converter of the module. Either 3.3-V or 5-V logic rails can be used. Maintain the ENA pin voltage below 5.5 V. After ENA pin voltage becomes above the enable threshold VEN_IR, UCC14240-Q1 enables, starts switching, goes through the soft-start process and delivers power to the secondary side. After ENA pin voltage falls below the disable threshold V_{EN_IF}, UCC14240-Q1 disables, stops switching.

The ENA pin can also be used to reset the UCC14240-Q1 device after it enters the protection safe-state mode. After a detected fault, the protection logic will latch off and place the device into a safe state. When all the faults are cleared, the ENA-pin can be used to clear the UCC14240-Q1 latch by toggling the ENA pin voltage below V_{EN_IF} for longer than 150 μs, then toggling back up to 3.3 V or 5 V. The device will then exit the latch-off mode and we initiate a soft-start. Figure 7-6 illustrates the latch-off reset timing.

The active-low power-good (PG) pin is an open-drain output that indicates (short) when the module has no fault and the output voltages are within ±10% of the output voltage regulation setpoints. Connect a pull-up resistor (> 1 kΩ) from PG pin to either a 5-V or 3.3-V logic rail. Maintain the PG pin voltage below 5.5 V without exceeding its recommended operating voltage. The logic of PG pin can be illustrated using Figure 7-7.