JAJSMY4C September   2021  – December 2022 UCC14240-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Electrical Characteristics
    9. 6.9  Safety Limiting Values
    10. 6.10 Insulation Characteristics
    11. 6.11 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Stage Operation
        1. 7.3.1.1 VDD-VEE Voltage Regulation
        2. 7.3.1.2 COM-VEE Voltage Regulation
        3. 7.3.1.3 Power Handling Capability
      2. 7.3.2 Output Voltage Soft Start
      3. 7.3.3 ENA and PG
      4. 7.3.4 Protection Functions
        1. 7.3.4.1 Input Undervoltage Lockout
        2. 7.3.4.2 Input Overvoltage Lockout
        3. 7.3.4.3 Output Overvoltage Protection
        4. 7.3.4.4 Overpower Protection
          1. 7.3.4.4.1 Output Undervoltage Protection
        5. 7.3.4.5 Overtemperature Protection
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Capacitor Selection
        2. 8.2.2.2 RLIM Resistor Selection
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  10. 10Mechanical, Packaging, and Orderable Information

8.2.2.1 Capacitor Selection

The UCC14240-Q1 device creates an isolated output VDD-VEE as its main output. The device also creates a second output COM-VEE, using VDD-VEE as its power source. Because both outputs are isolated from the input, and sharing VEE as the common reference point, the UCC14240-Q1 outputs can be configured as dual-output two-positive, dual-output two-negative, or dual-output one-positive and one-negative. UCC14240-Q1 output can also be used as a single positive output or single negative output.

When the module is configured as dual-output, one-positive output, one-negative output; it is very important to properly select the output capacitor ratios COUT2 and COUT3 to optimize the regulation and avoid causing an over-voltage or under-voltage fault.

Table 8-1 Calculated Capacitor Values
CAPACITORVALUE (µF)NOTES
CIN

10 + 0.1

Place a 10-μF and a 0.1-μF high-frequency decoupling capacitor in parallel close to VIN pins. A capacitance greater than 10uF can be used to reduce the voltage ripple when the series impedance from the voltage source to the VIN pins is large.

Optionally, connect a 330pF 0402 size high-frequency bypass ceramic capacitor close to analog VIN PIN 6 and GNDP PIN 5 when the input voltage ripple is large enough to interfere with the internal input voltage sense signal and the normal startup operation.

For extreme input ripple voltage cases, connect a 4.75-ohm filter resistor to power input, PIN7, and connect a 10-μF ceramic capacitor from analog VIN PIN 6, to power analog GNDP.

In most cases, the RC input filter is not needed. If the filter resistor is not placed, make sure both PIN 6 and PIN 7 are connected to input voltage.

COUT12.2 + 0.1Add a 2.2-μF and a 0.1-μF capacitor for high-frequency decoupling of (VDD – VEE). Place close to the VDD and VEE pins. A capacitance greater than 2.2uF can be used to reduce the output voltage ripple.
COUT2

See below

Bulk charge, decoupling output capacitors are required at the gate driver pins. The COUT2 and COUT3 capacitance ratio is important to optimize the dual output voltage divider accuracy during charge or discharge switching cycles.
COUT3See below

The selection of COUT2 and COUT3 is based on the gate charge requirement for the gate driver load, the charge balancing during the start-up, and the expected maximum current loading.

During the startup, the ratio between COUT2 and COUT3 must be equal to the ratio between (COM−VEE) and (VDD−COM) and offset by the loading current from VDD-COM and COM-VEE, to allow both COM to VEE and VDD to VEE voltages reaches steady state at the same time, as shown in Equation 1.

First calculate the COUT2 value based on the Gate charge of the power device QG_Total, whether IGBT or SiC power MOSFET, and the percent of voltage droop wanted during the turn-on of the gate with respect to the positive gate voltage applied, VDD to COM.

Equation 1. COUT2=QG_TotalPercent_Cdroop100×VVDD-COM
where

  • QG_Total is the total gate charge of the power switch

Then calculate the COUT3 value based on the output voltage ratios, the load current expected, and the variation of the output capacitors.

Equation 2. COUT3=COUT2×VVDD-COM×IMAX_POWER-I(COM-VEE)VCOM-VEE×IMAX_POWER-I(VDD-COM)

where the load IVDD-COM and ICOM-VEE are the load currents respectively, and the IMAX_POWER is the SOA Maximum Power (PMAX_SOA) divided by the VVDD-VEE output voltage.

Equation 3. I(VDD-COM)=IQ_Driver_VDD-COM+IOther_load_VDD-COM
Equation 4. I(COM-VEE)=IQ_Driver_COM-VEE+IOther_load_COM-VEE

where

  • I(VDD-COM) is the total current from VDD to COM, excluding average gate drive current.

  • I(COM-VEE) is the total current from COM to VEE, excluding average gate drive current.

  • IQ_DRIVER_VDD-COM is the maximum quiescent current of the gate driver from (VDD – COM), and any current pulled from VDD by external logic must be included.
  • IQ_DRIVER_COM-VEE is the maximum quiescent current of the gate driver from (COM – VEE),
  • IOther_load_VDD-COM is the maximum current pulled from VDD to COM by external logic.
  • IOther_load_COM-VEE is the maximum current pulled from COM to VEE by external logic.

and

Equation 5. IPOWER=PMAXVVDD-VEE

The approximate PMAX value can be extracted from the provided SOA curves at the respective ambient temperature.

Calculate COUT3 using worst case capacitor values based on expected variation, COUT3_maximum, and COUT3_Minimum . This action makes sure the capacitor ratio tends to push the COM-VEE voltage to a slightly lower value than the target regulation value during startup.

COUT2 and COUT3 are the total capacitance on the VDD and VEE outputs. They include the capacitors from both the isolated bias supply and the gate driver circuit.

The sizes of COUT2 and COUT3 are determined by the gate driver load gate charge and ripple voltage requirement. COUT1 can then be used to reduce the total ripple voltage and to soften the start-up time.