JAJSMY4C
September 2021 – December 2022
UCC14240-Q1
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Power Ratings
6.6
Insulation Specifications
6.7
Safety-Related Certifications
6.8
Electrical Characteristics
6.9
Safety Limiting Values
6.10
Insulation Characteristics
6.11
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Power Stage Operation
7.3.1.1
VDD-VEE Voltage Regulation
7.3.1.2
COM-VEE Voltage Regulation
7.3.1.3
Power Handling Capability
7.3.2
Output Voltage Soft Start
7.3.3
ENA and PG
7.3.4
Protection Functions
7.3.4.1
Input Undervoltage Lockout
7.3.4.2
Input Overvoltage Lockout
7.3.4.3
Output Overvoltage Protection
7.3.4.4
Overpower Protection
7.3.4.4.1
Output Undervoltage Protection
7.3.4.5
Overtemperature Protection
7.4
Device Functional Modes
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
Capacitor Selection
8.2.2.2
RLIM Resistor Selection
8.2.3
Application Curves
8.3
System Examples
8.4
Power Supply Recommendations
8.5
Layout
8.5.1
Layout Guidelines
8.5.2
Layout Example
9
Device and Documentation Support
9.1
Documentation Support
9.1.1
Related Documentation
9.2
ドキュメントの更新通知を受け取る方法
9.3
サポート・リソース
9.4
Trademarks
9.5
静電気放電に関する注意事項
9.6
用語集
10
Mechanical, Packaging, and Orderable Information
6.5
Power Ratings
V
VIN
= 24 V, C
IN
= 10µF, C
OUT
= 2.2 uF, T
J
= 150 °C, V
ENA
= 5 V
PARAMETER
TEST CONDITIONS
TYP VALUE
UNIT
P
D
Power dissipation
(VDD – VEE) = 25 V, P
VDD-VEE
= 2 W; (COM – VEE) = 5 V, No Load from (VDD - COM) or (COM - VEE)
1.65
W