JAJSNC1F September   2006  – January 2022 BQ2022A

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: DC
    6. 6.6 Switching Characteristics: AC
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 1024-Bit EPROM
      2. 7.3.2 EPROM Status Memory
      3. 7.3.3 Error Checking
      4. 7.3.4 Customizing the BQ2022A
      5. 7.3.5 Bus Termination
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1  Serial Communication
      2. 7.5.2  Initialization
      3. 7.5.3  ROM Commands
        1. 7.5.3.1 READ ROM Command
        2. 7.5.3.2 SKIP ROM Command
      4. 7.5.4  Memory/Status Function Commands
      5. 7.5.5  READ MEMORY Commands
        1. 7.5.5.1 READ MEMORY/Page CRC
        2. 7.5.5.2 READ MEMORY/Field CRC
      6. 7.5.6  WRITE MEMORY Command
      7. 7.5.7  READ STATUS Command
      8. 7.5.8  WRITE STATUS Command
      9. 7.5.9  PROGRAM PROFILE Byte
      10. 7.5.10 SDQ Signaling
      11. 7.5.11 RESET and PRESENCE PULSE
      12. 7.5.12 WRITE Bit
      13. 7.5.13 READ Bit
      14. 7.5.14 PROGRAM PULSE
      15. 7.5.15 IDLE
      16. 7.5.16 CRC Generation
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Programming Circuit Example
        2. 8.2.2.2 SDQ Master Best Practices
      3. 8.2.3 Application Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
      2. 11.2.2 Receiving Notification of Documentation Updates
    3. 11.3 Trademarks
    4. 11.4 サポート・リソース
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

READ MEMORY/Page CRC

To read memory and generate the CRC at the 32-byte page boundaries of the BQ2022A, the SKIP ROM command is followed by the READ MEMORY/Generate CRC command, C3h, followed by the address low byte and then the address high byte.

An 8-bit CRC of the command byte and address bytes is computed by the BQ2022A and read back by the host to confirm that the correct command word and starting address were received. If the CRC read by the host is incorrect, a reset pulse must be issued and the entire sequence must be repeated. If the CRC received by the host is correct, the host issues read time slots and receives data from the BQ2022A starting at the initial address and continuing until the end of a 32-byte page is reached. At that point, the host sends eight additional read time slots and receive an 8-bit CRC that is the result of shifting into the CRC generator all of the data bytes from the initial starting byte to the last byte of the current page. Once the 8-bit CRC has been received, data is again read from the 1024-bit EPROM data field starting at the next page. This sequence continues until the final page and its accompanying CRC are read by the host. Thus each page of data can be considered to be 33 bytes long, the 32 bytes of user-programmed EPROM data and an 8-bit CRC that gets generated automatically at the end of each page.

Figure 7-3 READ MEMORY/Page CRC
Initialization and SKIP ROM Command SequenceREAD MEMORY/Generate CRC CommandAddress Low ByteAddress High ByteRead and
Verify CRC
EPROM Memory and CRC Byte
Generated at 32-Byte Page
Boundaries
C3hA0A7A8A15
NOTE: Individual bytes of address and data are transmitted LSB first.