JAJSND1D July   2022  – April 2024 TPS1211-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Charge Pump and Gate Driver Output (VS, PU, PD, BST, SRC)
      2. 8.3.2 Capacitive Load Driving
        1. 8.3.2.1 FET Gate Slew Rate Control
        2. 8.3.2.2 Using Precharge FET - (with TPS12111-Q1 Only)
      3. 8.3.3 Overcurrent and Short-Circuit Protection
        1. 8.3.3.1 Overcurrent Protection with Auto-Retry
        2. 8.3.3.2 Overcurrent Protection with Latch-Off
        3. 8.3.3.3 Short-Circuit Protection
      4. 8.3.4 Analog Current Monitor Output (IMON)
      5. 8.3.5 Overvoltage (OV) and Undervoltage Protection (UVLO)
      6. 8.3.6 Remote Temperature Sensing and Protection (DIODE)
      7. 8.3.7 Output Reverse Polarity Protection
      8. 8.3.8 TPS1211x-Q1 as a Simple Gate Driver
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application: Driving Zonal Controller Loads on 12-V Line in Power Distribution Unit
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Typical Application: Reverse Polarity Protection with TPS12110-Q1
      1. 9.3.1 Design Requirements
      2. 9.3.2 External Component Selection
      3. 9.3.3 Application Curves
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 ドキュメントの更新通知を受け取る方法
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 静電気放電に関する注意事項
    5. 10.5 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.3.2.1 FET Gate Slew Rate Control

For limiting inrush current during turn-ON of the FET with capacitive loads, use R1, R2, C1 as shown in Figure 8-6. The R1 and C1 components slow down the voltage ramp rate at the gate of the FET. The FET source follows the gate voltage resulting in a controlled voltage ramp across the output capacitors.

TPS1211-Q1 Inrush Current Limiting with FET Gate Slew Rate ControlFigure 8-6 Inrush Current Limiting with FET Gate Slew Rate Control

Use the Equation 2 to calculate the inrush current during turn-ON of the FET.

Equation 2. TPS1211-Q1
Equation 3. TPS1211-Q1

Where,

CLOAD is the load capacitance, VBATT is the input voltage and Tcharge is the charge time, V(BST-SRC) is the charge pump voltage (12 V),

Use a damping resistor R2 (~ 10 Ω) in series with C1. Equation 3 can be used to compute required C1 value for a target inrush current. A 100-kΩ resistor for R1 can be a good starting point for calculations.

Connecting PD pin of TPS1211x-Q1 directly to the gate of the external FET ensures fast turn-OFF without any impact of R1 and C1 components.

C1 results in an additional loading on CBST to charge during turn-ON. Use Equation 4 to calculate the required CBST value.

Equation 4. TPS1211-Q1
Where, Qg(total) is the total gate charge of the FET.