JAJSNI4 December 2021 DAC11001B
PRODUCTION DATA
The 20-bit DAC11001B is a single-channel DAC. The unbuffered DAC output architecture is based on an R2R ladder that is designed to provide monotonicity and excellent linearity over wide reference and temperature ranges. This architecture provides a very low-noise (7 nV/√Hz) and fast-settling (1 µs) output. The DAC11001B also implements a deglitch circuit that enables low, code-independent glitch at the DAC output. The deglitch circuit is extremely useful for creating ultra-low, harmonic-distortion waveform generation.
The DAC11001B requires external reference voltages on REFPF and REFNF pins. The output of the DAC ranges from VREFNF to VREFPF. See Section 6.3 for VREFPFand VREFNF voltage ranges.
The DAC11001B also includes precision matched gain setting pins (ROFS, RCM, and RFB), Use these pins and an external op amp to scale the DAC output. The DAC11001B incorporates a power-on reset (POR) circuit to make sure that the DAC output powers up at zero scale, and remains at zero scale until a valid DAC command is issued. The DAC11001B uses a 4-wire serial interface that operates at clock rates of up to 50 MHz.