JAJSNI4 December 2021 DAC11001B
PRODUCTION DATA
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Read/Write | Address | EN_ TMP_ CAL |
RESERVED | TNH_MASK | RESERVED | ||||||||||
W | W | R/W-0h | W-0h | R/W-0h | W-0h | ||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSVD | LDAC MODE |
FSDO | ENALMP | DSDO | FSET | VREFVAL | RSVD | PDN | RESERVED | ||||||
W-0h | R/W-1h | R/W-0h | R/W-0h | R/W-1h | R/W-1h | R/W-2h | W-0h | R/W-0h | W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | Read/Write | W | N/A | Read when set to 1 or write when set to 0 |
30-24 | Address | W | N/A | 02h |
23 | EN_TMP_CAL | R/W | 0h | Enables and disables the temperature calibration
feature 0: Temperature calibration feature disabled (default) 1: Temperature calibration feature enabled |
22-20 | RESERVED | W | 0h | These bits are reserved. |
19-18 | TNH_MASK | R/W | 0h | Mask track and hold (TNH) circuit. This bit is writable
only when FSET = 0 [fast-settling mode] and DIS_TNH = 0
[track-and-hold enabled] 00: TNH masked for code jump > 214 (default) 01: TNH masked for code jump > 215 10: TNH masked for code jump > 213 11: TNH masked for code jump > 212 |
17-15 | RESERVED | W | 0h | These bits are reserved. |
14 | LDACMODE | R/W | 1h | Synchronous or asynchronous mode select bit 0: DAC output updated on SYNC rising edge 1: DAC updated on LDAC falling edge (default) |
13 | FSDO | R/W | 0h | Enable Fast SDO 0: Fast SDO disabled (Default) 1: Fast SDO enabled |
12 | ENALMP | R/W | 0h | Enable ALARM pin to be pulled low,
end of temperature calibration cycle 0: No alarm on the ALARM pin 1: Indicates end of temperature calibration cycle. ALARM pin pulled low. |
11 | DSDO | R/W | 1h | Enable SDO (for readback and daisy-chain) 1: SDO enabled (default) 0: SDO disabled |
10 | FSET | R/W | 1h | Fast-settling vs enhanced THD mode 0: Fast settling 1: Enhanced THD (default) |
9-6 | VREFVAL | R/W | 2h | Reference span value bits 0000: Invalid 0001: Invalid 0010: Reference span = 5 V ± 1.25 V (default) 0011: Reference span = 7.5 V ± 1.25 V 0100: Reference span = 10 V ± 1.25 V 0101: Reference span = 12.5 V ± 1.25 V 0110: Reference span = 15 V ± 1.25 V 0111: Reference span = 17.5 V ± 1.25 V 1000: Reference span = 20 V ± 1.25 V 1001: Reference span = 22.5 V ± 1.25 V 1010: Reference span = 25 V ± 1.25 V 1011: Reference span = 27.5 V± 1.25 V 1100: Reference span = 30 V ± 1.25 V |
5 | RESERVED | W | 0h | This bit is reserved. |
4 | PDN | R/W | 0h | Powers down and power up the DAC 0: DAC power up (default) 1: DAC power down |
3-0 | RESERVED | W | 0h | These bits are reserved. |