JAJSNI4 December 2021 DAC11001B
PRODUCTION DATA
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
fSCLK | SCLK frequency, 1.7 V ≤ IOVDD < 2.7 V | 33 | MHz | ||
SCLK frequency, 2.7 V ≤ IOVDD ≤ 5.5 V | 50 | ||||
tSCLKHIGH | SCLK high time, 1.7 V ≤ IOVDD < 2.7 V | 15 | ns | ||
SCLK high time, 2.7 V ≤ IOVDD ≤ 5.5 V | 10 | ||||
tSCLKLOW | SCLK low time, 1.7 V ≤ IOVDD < 2.7 V | 15 | ns | ||
SCLK low time, 2.7 V ≤ IOVDD ≤ 5.5 V | 10 | ||||
tSDIS | SDI setup, 1.7 V ≤ IOVDD < 2.7 V | 13 | ns | ||
SDI setup, 2.7 V ≤ IOVDD ≤ 5.5 V | 8 | ||||
tSDIH | SDI hold, 1.7 V ≤ IOVDD < 2.7 V | 13 | ns | ||
SDI hold, 2.7 V ≤ IOVDD ≤ 5.5 V | 8 | ||||
tCSS | SYNC falling edge to SCLK falling edge, 1.7 V ≤ IOVDD < 2.7 V | 23 | ns | ||
SYNC falling edge to SCLK falling edge, 2.7 V ≤ IOVDD ≤ 5.5 V | 18 | ||||
tCSH | SCLK falling edge to SYNC rising edge, 1.7 V ≤ IOVDD < 2.7 V | 15 | ns | ||
SCLK falling edge to SYNC rising edge, 2.7 V ≤ IOVDD ≤ 5.5 V | 10 | ||||
tCSHIGH | SYNC high time, 1.7 V ≤ IOVDD < 2.7 V | 55 | ns | ||
SYNC high time, 2.7 V ≤ IOVDD ≤ 5.5 V | 50 | ||||
tCSIGNORE | SCLK falling edge to SYNC ignore, 1.7 V ≤ IOVDD < 2.7 V | 10 | ns | ||
SCLK falling edge to SYNC ignore, 2.7 V ≤ IOVDD ≤ 5.5 V | 5 | ||||
tLDACSL | Synchronous update: SYNC rising edge to LDAC falling edge, 1.7 V ≤ IOVDD < 2.7 V |
50 | ns | ||
Synchronous update: SYNC rising edge to LDAC falling edge, 2.7 V ≤ IOVDD ≤ 5.5 V |
50 | ||||
tLDACW | LDAC low time, 1.7 V ≤ IOVDD < 2.7 V | 20 | ns | ||
LDAC low time, 2.7 V ≤ IOVDD ≤ 5.5 V | 20 | ||||
tCLRW | CLR low time, 1.7 V ≤ IOVDD < 2.7 V | 20 | ns | ||
CLR low time, 2.7 V ≤ IOVDD ≤ 5.5 V | 20 |