JAJSNN2B October   2023  – July 2024 UCC25660

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Power Proportional Control
        1. 7.3.1.1 Voltage Feedforward
      2. 7.3.2 VCR Synthesizer
      3. 7.3.3 Feedback Chain (Control Input)
      4. 7.3.4 Adaptive Dead-Time
      5. 7.3.5 Input Voltage Sensing
        1. 7.3.5.1 Brown in and Brown out Tresholds and Options
        2. 7.3.5.2 Output OVP and External OTP
      6. 7.3.6 Resonant Tank Current Sensing
    4. 7.4 Protections
      1. 7.4.1 Zero Current Switching (ZCS) Protection
      2. 7.4.2 Minimum Current Turn-off During Soft Start
      3. 7.4.3 Cycle by Cycle Current Limit and Short Circuit Protection
      4. 7.4.4 Overload (OLP) Protection
      5. 7.4.5 VCC OVP Protection
    5. 7.5 Device Functional Modes
      1. 7.5.1 Startup
        1. 7.5.1.1 With HV Startup
        2. 7.5.1.2 Without HV Startup
      2. 7.5.2 Soft Start Ramp
        1. 7.5.2.1 Startup Transition to Regulation
      3. 7.5.3 Light Load Management
        1. 7.5.3.1 Operating Modes (Burst Pattern)
        2. 7.5.3.2 Mode Transition Management
        3. 7.5.3.3 Burst Mode Threshold Programming
        4. 7.5.3.4 PFC On/Off
      4. 7.5.4 X-Capacitor Discharge
        1. 7.5.4.1 Detecting Through HV Pin Only
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  LLC Power Stage Requirements
        2. 8.2.2.2  LLC Gain Range
        3. 8.2.2.3  Select Ln and Qe
        4. 8.2.2.4  Determine Equivalent Load Resistance
        5. 8.2.2.5  Determine Component Parameters for LLC Resonant Circuit
        6. 8.2.2.6  LLC Primary-Side Currents
        7. 8.2.2.7  LLC Secondary-Side Currents
        8. 8.2.2.8  LLC Transformer
        9. 8.2.2.9  LLC Resonant Inductor
        10. 8.2.2.10 LLC Resonant Capacitor
        11. 8.2.2.11 LLC Primary-Side MOSFETs
        12. 8.2.2.12 Design Considerations for Adaptive Dead-Time
        13. 8.2.2.13 LLC Rectifier Diodes
        14. 8.2.2.14 LLC Output Capacitors
        15. 8.2.2.15 HV Pin Series Resistors
        16. 8.2.2.16 BLK Pin Voltage Divider
        17. 8.2.2.17 ISNS Pin Differentiator
        18. 8.2.2.18 TSET Pin
        19. 8.2.2.19 OVP/OTP Pin
        20. 8.2.2.20 Burst Mode Programming
        21. 8.2.2.21 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 VCCP Pin Capacitor
      2. 8.3.2 Boot Capacitor
      3. 8.3.3 V5P Pin Capacitor
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
        1. 8.4.2.1 Schematics
        2. 8.4.2.2 Schematics
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

7.5.1.1 With HV Startup

First time startup sequence

  1. When AC is plugged in, voltage is applied on HV pin. If VCCP voltage is below VCCShort, VCCP pin is charged with IVCC_Charge_Low. If VCCP voltage is higher than VCCShort, VCCP pin is charged with IVCC_Charge_High.
  2. When VCCP voltage is higher than VCCUVLOr, an internal LDO regulates the V5P voltage untill the device initialization is complete.
  3. V5P is established. LL pin & TSET pin are used for burst mode and internal VCR Synthesizer programming.
  4. If the HV startup option is enabled, the TSET pin outputs high (means PFC OFF) to prevent PFC from turning on before VCCP is full established.
  5. When VCCP is higher than VCCStartSelf, HV charge current stops. LLC startup process begins. TSET voltage is kept lower than 1V, allowing PFC to startup.
  6. If during stages 3 and 4, VCCP voltage drops below VCCReStartJfet, HV charge current enables again and VCCP gets charged with IVCC_Charge_High
  7. Once LLC finishes startup, HV charge current is disabled until VCCP drops below VCCReStartJfet.
  8. During normal operation if the VCCP voltage falls below VCCStopSwitching, a fault occurs and UCC25660x ファミリ shuts down. Normal restart sequence is then followed.

Restart sequence

  1. After a fault is detected, UCC25660x ファミリ shuts down. For fault retry mode, after 1s idle time, UCC25660x ファミリ retries (TSET outputs high when VCCP is still higher than VCCUVLOf).
  2. if VCCP voltage is below VCCShort, VCCP pin is charged with IVCC_Charge_Low. If VCCP voltage is higher than VCCShort, VCCP pin is charged with IVCC_Charge_High. If VCCP pin voltage is higher than VCCStartSelf, HV startup is not enabled (Phase I is skipped). V5P is established and LL pin is released for burst mode programming.
UCC25660 Startup Sequence for “HV Startup” Feature Enabled Figure 7-13 Startup Sequence for “HV Startup” Feature Enabled