JAJSNW1B October   2023  – June 2024 TPSM843620

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics (Module)
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  VIN Pins and VIN UVLO
      2. 6.3.2  Enable and Adjustable UVLO
      3. 6.3.3  Adjusting the Output Voltage
      4. 6.3.4  Switching Frequency Selection
      5. 6.3.5  Switching Frequency Synchronization to an External Clock
        1. 6.3.5.1 Internal PWM Oscillator Frequency
        2. 6.3.5.2 Loss of Synchronization
        3. 6.3.5.3 Interfacing the SYNC/FSEL Pin
      6. 6.3.6  Ramp Amplitude Selection
      7. 6.3.7  Soft Start and Prebiased Output Start-Up
      8. 6.3.8  Mode Pin
      9. 6.3.9  Power Good (PGOOD)
      10. 6.3.10 Current Protection
        1. 6.3.10.1 Positive Inductor Current Protection
        2. 6.3.10.2 Negative Inductor Current Protection
      11. 6.3.11 Output Overvoltage and Undervoltage Protection
      12. 6.3.12 Overtemperature Protection
      13. 6.3.13 Output Voltage Discharge
    4. 6.4 Device Functional Modes
      1. 6.4.1 Forced Continuous-Conduction Mode
      2. 6.4.2 Discontinuous Conduction Mode During Soft Start
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 1.0V Output, 1MHz Application
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1  Switching Frequency
          2. 7.2.1.2.2  Output Inductor Selection
          3. 7.2.1.2.3  Output Capacitor
          4. 7.2.1.2.4  Input Capacitor
          5. 7.2.1.2.5  Adjustable Undervoltage Lockout
          6. 7.2.1.2.6  Output Voltage Resistors Selection
          7. 7.2.1.2.7  Bootstrap Capacitor Selection
          8. 7.2.1.2.8  BP5 Capacitor Selection
          9. 7.2.1.2.9  PGOOD Pullup Resistor
          10. 7.2.1.2.10 Current Limit Selection
          11. 7.2.1.2.11 Soft-Start Time Selection
          12. 7.2.1.2.12 Ramp Selection and Control Loop Stability
          13. 7.2.1.2.13 MODE Pin
        3. 7.2.1.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
        1. 7.4.2.1 Thermal Performance
  9. 8 Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

6.3.5.2 Loss of Synchronization

If at any time during operation, there is a loss of synchronization, the device defaults to the internal PWM oscillator frequency until the synchronization clock returns. After the clock is no longer present, the device switches at 70% of the internal clock frequency for four consecutive cycles. After four consecutive cycles without clock pulses, the device operates at the normal internal PWM oscillator frequency. This action is demonstrated in Figure 6-4.

TPSM843620 Clock Synchronization TransitionsFigure 6-4 Clock Synchronization Transitions