JAJSOA3B February   2023  – June 2024 TPS25948

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Undervoltage Lockout (UVLO and UVP)
      2. 7.3.2 Overvoltage Lockout (OVLO)
      3. 7.3.3 Inrush Current, Overcurrent, and Short Circuit Protection
        1. 7.3.3.1 Slew Rate (dVdt) and Inrush Current Control
        2. 7.3.3.2 Active Current Limiting
        3. 7.3.3.3 Short-Circuit Protection
      4. 7.3.4 Analog Load Current Monitor
      5. 7.3.5 Reverse Current Protection
      6. 7.3.6 Overtemperature Protection (OTP)
      7. 7.3.7 Fault Response and Indication (FLT)
      8. 7.3.8 Supply Good Indication (SPLYGD/SPLYGD)
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Single Device, Self-Controlled
    3. 8.3 Typical Application
      1. 8.3.1 Design Requirements
      2. 8.3.2 Detailed Design Procedure
        1. 8.3.2.1 Setting Overvoltage Threshold
        2. 8.3.2.2 Setting Output Voltage Rise Time (tR)
        3. 8.3.2.3 Setting Overcurrent Threshold (ILIM)
        4. 8.3.2.4 Setting Overcurrent Blanking Interval (tITIMER)
      3. 8.3.3 Application Curves
    4. 8.4 Active ORing
    5. 8.5 Priority Power MUXing
    6. 8.6 Parallel Operation
    7. 8.7 USB PD Port Protection
    8. 8.8 Power Supply Recommendations
      1. 8.8.1 Transient Protection
      2. 8.8.2 Output Short-Circuit Measurements
    9. 8.9 Layout
      1. 8.9.1 Layout Guidelines
      2. 8.9.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.3.7 Fault Response and Indication (FLT)

The following table summarizes the device response to various fault conditions. Additionally, an active low external fault indication (FLT) pin is available on the TPS259480x variants.

Table 7-2 Fault Summary
EventProtection ResponseFault Latched InternallyFLT Pin Status (1)FLT Assertion Delay(1)

Overtemperature

Shutdown

Y

L

Undervoltage (UVP or UVLO)

Shutdown

N

H

Input Overvoltage

Shutdown

N

H

Transient Overcurrent (ILIM < IOUT < 2 × ILIM or IFFT for duration less than tITIMER)

None

N

H

Persistent OvercurrentCurrent Limit

N

L

tITIMER

Output Short-Circuit to GND

Circuit Breaker followed by Current Limit

N

H

ILM Pin Open

(During Steady State)

Shutdown

N

H

ILM Pin Shorted to GND

Shutdown

Y

L

Reverse Current ((VOUT - VIN) > VREVTH)

Reverse Current Blocking

N

H

(1) Applicable to TPS259480x variants only.

Faults which are latched internally can be cleared either by power cycling the part (pulling VIN to 0 V) or by pulling the EN/UVLO pin voltage below VSD(F). This also releases the FLT pin pull-down for the TPS259480x variants and resets the tRST timer for the TPS25948xA (auto-retry) variants.

During a latched fault, pulling the EN/UVLO just below the UVLO threshold has no impact on the device. This is true for both TPS25948xL (latch-off) and TPS25948xA (auto-retry) variants.

For TPS25948xA (auto-retry) variants, on expiry of the tRST timer after a fault, the device restarts automatically and the FLT pin is de-asserted (TPS259480A variant).