JAJSOX0A March   2024  – June 2024 ADS127L18

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
  7. 6 Parameter Measurement Information
    1. 6.1  Offset Error Measurement
    2. 6.2  Offset Drift Measurement
    3. 6.3  Gain Error Measurement
    4. 6.4  Gain Drift Measurement
    5. 6.5  NMRR Measurement
    6. 6.6  CMRR Measurement
    7. 6.7  PSRR Measurement
    8. 6.8  SNR Measurement
    9. 6.9  INL Error Measurement
    10. 6.10 THD Measurement
    11. 6.11 IMD Measurement
    12. 6.12 SFDR Measurement
    13. 6.13 Noise Performance
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs (AINP, AINN)
        1. 7.3.1.1 Input Range
      2. 7.3.2 Reference Voltage (REFP, REFN)
        1. 7.3.2.1 Reference Voltage Range
      3. 7.3.3 Clock Operation
        1. 7.3.3.1 Internal Oscillator
        2. 7.3.3.2 External Clock
      4. 7.3.4 Power Supplies
        1. 7.3.4.1 AVDD1 and AVSS
        2. 7.3.4.2 AVDD2
        3. 7.3.4.3 IOVDD
        4. 7.3.4.4 Power-On Reset (POR)
        5. 7.3.4.5 CAPA and CAPD
      5. 7.3.5 VCM Output Voltage
      6. 7.3.6 GPIO
      7. 7.3.7 Modulator
      8. 7.3.8 Digital Filter
        1. 7.3.8.1 Wideband Filter
      9. 7.3.9 Low-Latency Filter (Sinc)
        1. 7.3.9.1 Sinc4 Filter
        2. 7.3.9.2 Sinc4 + Sinc1 Cascade Filter
        3. 7.3.9.3 Sinc3 Filter
        4. 7.3.9.4 Sinc3 + Sinc1 Filter
    4. 7.4 Device Functional Modes
      1. 7.4.1  Speed Modes
      2. 7.4.2  Synchronization
        1. 7.4.2.1 Synchronized Control Mode
        2. 7.4.2.2 Start/Stop Control Mode
      3. 7.4.3  Digital Filter Settling
      4. 7.4.4  Conversion-Start Delay Time
      5. 7.4.5  Data Averaging
      6. 7.4.6  Calibration
        1. 7.4.6.1 Offset Calibration Registers
        2. 7.4.6.2 Gain Calibration Registers
        3. 7.4.6.3 Calibration Procedure
      7. 7.4.7  Reset
        1. 7.4.7.1 RESET Pin
        2. 7.4.7.2 Reset by SPI Register
        3. 7.4.7.3 Reset by SPI Input Pattern
      8. 7.4.8  Power-Down
      9. 7.4.9  Idle and Standby Modes
      10. 7.4.10 Diagnostics
        1. 7.4.10.1 ERROR Pin and ERR_FLAG Bit
        2. 7.4.10.2 Clock Counter
        3. 7.4.10.3 SCLK Counter
        4. 7.4.10.4 Frame-Sync CRC
        5. 7.4.10.5 SPI CRC
        6. 7.4.10.6 Register Map CRC
        7. 7.4.10.7 Self Test
      11. 7.4.11 Frame-Sync Data Port
        1. 7.4.11.1 FSYNC Pin
        2. 7.4.11.2 DCLK Pin
        3. 7.4.11.3 DOUT Pins
        4. 7.4.11.4 DIN Pins
        5. 7.4.11.5 Time Division Multiplexing
        6. 7.4.11.6 Daisy Chain
        7. 7.4.11.7 Data Packet
        8. 7.4.11.8 STATUS_DP Header
        9. 7.4.11.9 Data Port Timing Adjustment
    5. 7.5 Programming
      1. 7.5.1 Hardware Programming
      2. 7.5.2 SPI Programming
        1. 7.5.2.1 Chip Select (CS)
        2. 7.5.2.2 Serial Clock (SCLK)
        3. 7.5.2.3 Serial Data Input (SDI)
        4. 7.5.2.4 Serial Data Output (SDO)
      3. 7.5.3 SPI Frame
      4. 7.5.4 SPI Commands
        1. 7.5.4.1 Read Register Command
        2. 7.5.4.2 Write Register Command
      5. 7.5.5 SPI Daisy-Chain
  9. 8 Register Map
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Input Driver
      2. 9.1.2 Antialias Filter
      3. 9.1.3 Reference Voltage
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data

7.4.11.2 DCLK Pin

The DCLK pin is the bit-clock output signal that shifts data out from the frame-sync port. DOUT channel data are updated on the falling edge of DCLK and are latched by the host on the rising edge.

The DCLK frequency is derived from the ADC clock through a programmable DCLK divider. See the Clock Operation section for details of the DCLK divider. Make sure the DCLK signal frequency is fast enough to transmit the channel data within one conversion period (FSYNC clock period), otherwise data are lost. Equation 22 shows how to derive the minimum required DCLK frequency.

Equation 22. fDCLK ≥ fDATA × TDM factor × Data packet size

where:

  • fDATA = Data rate (SPS).
  • TDM factor = Time division multiplexing factor. This factor is equal to the channels per DOUT pin (1, 2, 4, or 8); see the Time Division Multiplexing section for more details.
  • Data packet size = Number of bits in a data packet. See the Data Packet section for more details.

Table 7-18 shows various examples of DCLK frequencies. The example in the third row is for a 512kSPS data rate, max-speed mode, a TDM factor of 4, and a 24-bit data packet size. The TDM factor equals four channels per DOUT pin. The minimum DCLK signal frequency to shift out the data in one data period is 49.152MHz (512kSPS × 4 × 24). Using 65.536MHz for CLKIN satisfies the minimum DCLK frequency. With the CLK divider = 2, the 32.768MHz CLK frequency is derived for ADC clock operation.

Table 7-13 DCLK Frequency Requirements
SPEED MODE DATA RATE
(kSPS)		 BITS PER DOUT PIN DCLK MIN
(MHz)		 CLKIN INPUT
(MHZ)		 CLK DIVIDER ADC CLOCK
(MHz)		 DCLK DIVIDER DCLK ACTUAL (MHz)
Max 1365.3 48 (2 ch × 24 bits) 65.536 65.536 2 32.768 1 65.536
Max 512 24 (1 ch × 24 bits) 12.288 32.768 1 32.768 2 16.384
Max 512 96 (4 ch × 24 bits) 49.152 65.536 2 32.768 1 65.536
High 400 96 (4 ch × 24 bits) 38.400 51.200 2 25.600 1 51.200
Mid 200 160 (4 ch × 40 bits) 32.000 38.400 3 12.800 1 38.400
Low 50 320 (8 ch × 40 bits) 16.000 25.600 8 3.200 1 25.600

When daisy-chaining the frame-sync port, the maximum DCLK signal frequency is limited; see the Specifications section.