Assuming a vaild input source is attached to IN or USB, as soon as a deeply discharged or shorted battery is attached to the BAT pin, (V_BAT < V_BATSHRT), the BQ2416xx applies I_BATSHRT to close the pack protector switch and bring the battery voltage up to acceptable charging levels. During this time, the battery FET is linearly regulated and the system output is regulated to V_SYS(REG). Once the battery rises above V_BATSHRT, the charge current is regulated to the value set in the I²C register. The battery FET is linearly regulated to maintain the system voltage at V_SYS(REG). Under normal conditions, the time spent in this region is a very short percentage of the total charging time, so the linear regulation of the charge current does not affect the overall charging efficiency for very long. If the die temperature does rise, the thermal regulation circuit reduces the charge current to maintain a die temperature less than 120°C. If the current limit for the SYS output is reached (limited by the input current limit, or V_{IN_DPM}), the SYS output drops to the V_MINSYS output voltage. When this happens, the charge current is reduced to provide the system with all the current that is needed while maintaining the minimum system voltage. If the charge current is reduced to 0mA, pulling further current from SYS causes the output to fall to the battery voltage and enter supplement mode. (See the Dynamic Power Path Management section for more details.)

Once the battery is charged enough so that the system voltage begins to rise above V_SYS(REG), the battery FET is turned on fully and the battery is charged with the full programmed charge current set by the I²C interface, I_CHARGE. The slew rate for the fast-charge current is controlled to minimize current and voltage overshoot during transients. The charge current is regulated to I_CHARGE until the battery is charged to the regulation voltage. As the battery voltage rises above VRCH, the battery regulation loop is activated. This may result in a small step down in the charge current as the loops transition between the charge current and charge voltage loops. As the battery voltage charges up to the regulation voltage, V_BATREG, the charge current is tapered down as shown in Figure 8-1 while the SYS output remains connected to the battery. The voltage between the BAT and PGND pins is regulated to V_BATREG. The BQ2416xx is a fixed single-cell voltage version, with adjustable regulation voltage (3.5 V to 4.44 V), programmed using the I²C interface.

The BQ2416xx monitors the charging current during the voltage-regulation phase. If the battery voltage is above the recharge threshold and the charge current has naturally tapered down to and remains below termination threshold, I_TERM, (without disturbance from events like supplement mode) for 32 ms, the charger terminates charge, turns off the battery charging FET and enters battery detection. Termination is disabled when the charge current is reduced by a loop other than the voltage regulation loop or the input current limit is set to 100 mA. For example, when the BQ2416xx is in half charge due to TS function, reverse boost protection is active, LOW_CHG bit is set, or the thermal regulation, V_INDPM or input current loops are active, termination will not occur. This prevents false termination events. During termination, the system output is regulated to the V_SYS(REG) and supports the full current available from the input and the battery supplement mode is available. (See the Dynamic Power Path Management section for more details.) The termination current level is programmable. When setting the termination threshold less than 150mA, the reverse boost protection may trip falsely with load transients and very fully charged batteries. This will prevent termination while in the reverse boost protection and may extend charge time. To disable the charge current termination, the host sets the charge termination bit (TE) of charge control register to 0, refer to I²C section for details.

A new charge cycle is initiated if CD is low when either

1. V_SUPPLY rises above UVLO while a battery with V_BAT < V_BATREG - V_RCH is attached or
2. a battery with V_BAT < V_BATREG - V_RCH is attached while V_SUPPLY is above UVLO.

With V_SUPPLY above UVLO and V(BAT) < V_BOVP, a recharge cycle is initiated when one of the following conditions is detected:

1. The battery voltage falls below the V_BAT(REG)-V_RCH threshold.
2. CE bit toggle or RESET bit toggle
3. Supplement mode event occurs
4. CD pin or HI-Z bit toggle

V_BAT(REG) should never be programmed less than V_BAT. If the battery is ever 5% above the regulation threshold, the battery OVP circuit shuts the PWM converter off immediately and the battery FET is turned on to discharge the battery to safe operating levels. If the battery OVP condition exists for the 1ms deglitch, a battery OVP fault is reported in the I²C status registers. The battery OVP fault is cleared when the battery voltage discharges below V_RCH or if the IC enters hi-impedance mode (HZ_MODE=1 or CD=1). Always write BQ2416xx to high impedance mode before changing V_BATREG to clear BOVP condition to ensure proper operation.

If the battery voltage is ever greater than VBATREG (for example, when an almost fully charged battery enters the JEITA WARM state due to the TS pin) but less than V_BOVP, the reverse boost protection circuitry may activate as explained later in this data sheet. If the battery is ever above V_BOVP, the buck converter turns off and the internal battery FET is turned on. This prevents further overcharging of the battery and allows the battery to discharge to safe operating levels. The battery OVP event does not clear until the battery voltage falls below V_RCH.